參數(shù)資料
型號: SST89C58RC-40-I-TQJE
廠商: Microchip Technology
文件頁數(shù): 26/88頁
文件大小: 0K
描述: IC MCU 8BIT FLASH 40TQFP
標準包裝: 160
系列: FlashFlex®
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,I²C,SMBus,UART/USART
外圍設備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
2011 Silicon Storage Technology, Inc.
DS25100A
12/11
32
FlashFlex MCU
SST89C58RC
Data Sheet
A Microchip Technology Company
Flash Memory Programming
The device internal flash memory can be programmed or erased using In-Application Programming
(IAP).
Product Identification
The Read-ID command accesses the Signature Bytes that identify the device and the manufacturer as
SST. External programmers primarily use these Signature Bytes in the selection of programming algo-
rithms.
In-Application Programming
The IAP/ISP functions are issued via the SST mail box scheme. Detailed flash block operations are
performed by the flash control unit. While the flash control executes IAP commands, the CPU is on
hold since there is only one physical flash block in the SST89C58RC devices. When IAP commands
finish, the CPU can resume execution of the application code. So the application code needs to turn off
the interrupt or turn off the peripheral modules before it issues IAP commands since the CPU cannot
respond to the interrupt or poll the SFR status.
The IAP supports the following commands:
1.
Chip-Erase
2.
Partition0-Erase
3.
Sector-Erase
4.
Byte-Program
5.
Byte-Verify
6.
Secure Page (Page-Level Security Command)
Secure-Page 0, 1, 2, 3, 4
7.
Secure Chip (Chip-Level Security Command)
Disable-Extern-IAP
Disable-Extern-Boot
Disable-Extern-MOVC
Disable-Extern-Host-Cmd
8.
Enable Clock Double
9.
Boot Option Command
Boot-From User-Vector
Boot-From-Zero
Set-User-Boot-Vector
Table 11:Product Identification
Address
Data
Manufacturer’s ID
30H
BFH
Device ID
31H
F7H
Device ID (extended)
32H
A0H
T0-0.0 25100
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