參數(shù)資料
型號(hào)： SST89V58RD2-33-C-NJE
廠商： Microchip Technology
文件頁數(shù)： 41/92頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 40KB FLASH 44PLCC
標(biāo)準(zhǔn)包裝： 26
系列： FlashFlex®
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 36
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 8K x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
2011 Silicon Storage Technology, Inc.
DS25087A
10/11
46
FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Not Recommended for New Designs
A Microchip Technology Company
Serial I/O
Full-Duplex, Enhanced UART
The device serial I/O port is a full-duplex port that allows data to be transmitted and received simulta-
neously in hardware by the transmit and receive registers, respectively, while the software is perform-
ing other tasks. The transmit and receive registers are both located in the Serial Data Buffer (SBUF)
special function register. Writing to the SBUF register loads the transmit register, and reading from the
SBUF register obtains the contents of the receive register.
The UART has four modes of operation which are selected by the Serial Port Mode Specifier (SM0 and
SM1) bits of the Serial Port Control (SCON) special function register. In all four modes, transmission is
initiated by any instruction that uses the SBUF register as a destination register. Reception is initiated
in mode 0 when the Receive Interrupt (RI) flag bit of the Serial Port Control (SCON) SFR is cleared
and the Reception Enable/ Disable (REN) bit of the SCON register is set. Reception is initiated in the
other modes by the incoming start bit if the REN bit of the SCON register is set.
Framing Error Detection
Framing Error Detection is a feature, which allows the receiving controller to check for valid stop bits in
modes 1, 2, or 3. Missing stops bits can be caused by noise in serial lines or from simultaneous trans-
mission by two CPUs.
Framing Error Detection is selected by going to the PCON register and changing SMOD0 = 1 (see Fig-
ure 17). If a stop bit is missing, the Framing Error bit (FE) will be set. Software may examine the FE bit
after each reception to check for data errors. After the FE bit has been set, it can only be cleared by
software. Valid stop bits do not clear FE. When FE is enabled, RI rises on the stop bit, instead of the
last data bit (see Figure 18 and Figure 19).
Figure 17:Framing Error Block Diagram
1255 F16.0
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
SMOD0
SMOD1
POF
GF1
GF0
PD
IDL
SCON
(98H)
PCON
(87H)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD0 = 0)
To UART framing error control
BOF
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