參數(shù)資料
型號(hào)： SST89V58RD2-33-C-NJE
廠商： Microchip Technology
文件頁數(shù)： 49/92頁
文件大小： 0K
描述： IC MCU 8BIT 40KB FLASH 44PLCC
標(biāo)準(zhǔn)包裝： 26
系列： FlashFlex®
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 36
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 8K x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
2011 Silicon Storage Technology, Inc.
DS25087A
10/11
53
FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Not Recommended for New Designs
A Microchip Technology Company
Watchdog Timer
The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software
deadlock and automatic recovery.
To protect the system against software deadlock, the user software must refresh the WDT within a
user-defined time period. If the software fails to do this periodical refresh, an internal hardware reset
will be initiated if enabled (WDRE= 1). The software can be designed such that the WDT times out if
the program does not work properly.
The WDT in the device uses the system clock (XTAL1) as its time base. So strictly speaking, it is a
watchdog counter rather than a watchdog timer. The WDT register will increment every 344,064 crystal
clocks. The upper 8-bits of the time base register (WDTD) are used as the reload register of the WDT.
The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User software can clear
WDTS by writing “1” to it.
Figure 23 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control watchdog timer
operation. During idle mode, WDT operation is temporarily suspended, and resumes upon an interrupt
exit from idle.
The time-out period of the WDT is calculated as follows:
Period = (255 - WDTD) * 344064 * 1/fCLK (XTAL1)
where WDTD is the value loaded into the WDTD register and fOSC is the oscillator frequency.
Figure 23:Block Diagram of Programmable Watchdog Timer
1255 F22.0
WDT Upper Byte
WDT Reset
Internal Reset
344064
clks
Counter
CLK (XTAL1)
Ext. RST
WDTC
WDTD
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