參數(shù)資料
型號: SST89V58RD2-33-C-NJE
廠商: Microchip Technology
文件頁數(shù): 52/92頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 40KB FLASH 44PLCC
標(biāo)準(zhǔn)包裝: 26
系列: FlashFlex®
核心處理器: 8051
芯體尺寸: 8-位
速度: 33MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 8K x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
2011 Silicon Storage Technology, Inc.
DS25087A
10/11
56
FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Not Recommended for New Designs
A Microchip Technology Company
an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared
by software. Each module has its own timer interrupt or capture interrupt flag (CCF0 for module 0,
CCF4 for module 4, etc.). They are set when either a match or capture occurs. These flags can only be
cleared by software. (See “PCA Timer/Counter Control Register (CCON)” on page 26.)
Compare/Capture Modules
Each PCA module has an associated SFR with it. These registers are: CCAPM0 for module 0,
CCAPM1 for module 1, etc. Refer to “PCA Compare/Capture Module Mode Register (CCAPMn)” on
page 28 for details. The registers each contain 7 bits which are used to control the mode each module
will operate in. The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on module) will enable
the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs. PWM
(CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set, causes
the CEX output associated with the module to toggle when there is a match between the PCA counter
and the module’s capture/compare register. When there is a match between the PCA counter and the
module’s capture/compare register, the MATn (CCAPMn.3) and the CCFn bit in the CCON register to
be set.
Bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine whether the capture input will be active on
a positive edge or negative edge. The CAPN bit enables the negative edge that a capture input will be
active on, and the CAPP bit enables the positive edge. When both bits are set, both edges will be
enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6)
when set, enables the comparator function. Table 21 shows the CCAPMn settings for the various PCA
functions.
There are two additional register associated with each of the PCA modules: CCAPnH and CCAPnL.
They are registers that hold the 16-bit count value when a capture occurs or a compare occurs. When
a module is used in PWM mode, these registers are used to control the duty cycle of the output. See
Figure 24.
Table 20: PCA High and Low Register Compare/Capture Modules
Symbol
Description
Direct
Address
Bit Address, Symbol, or Alternative Port Function
RESET
Value
MSB
LSB
CCAP0H PCA Module 0
Compare/Capture
Registers
FAH
CCAP0H[7:0]
00H
CCAP0L
EAH
CCAP0L[7:0]
00H
CCAP1H PCA Module 1
Compare/Capture
Registers
FBH
CCAP1H[7:0]
00H
CCAP1L
EBH
CCAP1L[7:0]
00H
CCAP2H PCA Module 2
Compare/Capture
Registers
FCH
CCAP2H[7:0]
00H
CCAP2L
ECH
CCAP2L[7:0]
00H
CCAP3H PCA Module 3
Compare/Capture
Registers
FDH
CCAP3H[7:0]
00H
CCAP3L
EDH
CCAP3L[7:0]
00H
CCAP4H PCA Module 4
Compare/Capture
Registers
FEH
CCAP4H[7:0]
00H
CCAP4L
EEH
CCAP4L[7:0]
00H
T0-0.0 25087
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