參數(shù)資料
型號: SST89V58RD2-33-I-NJE
廠商: Microchip Technology
文件頁數(shù): 61/92頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 40KB FLASH 44PLCC
標準包裝: 27
系列: FlashFlex®
核心處理器: 8051
芯體尺寸: 8-位
速度: 33MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 8K x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
2011 Silicon Storage Technology, Inc.
DS25087A
10/11
64
FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Not Recommended for New Designs
A Microchip Technology Company
Security Lock
The security lock protects against software piracy and prevents the contents of the flash from being
read by unauthorized parties. It also protects against code corruption resulting from accidental erasing
and programming to the internal flash memory. There are two different types of security locks in the
device security lock system: hard lock and SoftLock.
Hard Lock
When hard lock is activated, MOVC or IAP instructions executed from an unlocked or soft locked pro-
gram address space, are disabled from reading code bytes in hard locked memory blocks (See Table
25). Hard lock can either lock both flash memory blocks or just lock the 8 KByte flash memory block
(Block 1). All external host and IAP commands except for Chip-Erase are ignored for memory blocks
that are hard locked.
SoftLock
SoftLock allows flash contents to be altered under a secure environment. This lock option allows the
user to update program code in the soft locked memory block through in-application programming
mode under a predetermined secure environment. For example, if Block 1 (8K) memory block is locked
(hard locked or soft locked), and Block 0 memory block is soft locked, code residing in Block 1 can pro-
gram Block 0. The following IAP mode commands issued through the command mailbox register,
SFCM, executed from a Locked (hard locked or soft locked) block, can be operated on a soft locked
block: Block-Erase, Sector-Erase, Byte-Program and Byte-Verify.
In external host mode, SoftLock behaves the same as a hard lock.
Security Lock Status
The three bits that indicate the device security lock status are located in SFST[7:5]. As shown in Figure
30 and Table 24, the three security lock bits control the lock status of the primary and secondary blocks
of memory. There are four distinct levels of security lock status. In the first level, none of the security
lock bits are programmed and both blocks are unlocked. In the second level, although both blocks are
now locked and cannot be programmed, they are available for read operation via Byte-Verify. In the
third level, three different options are available: Block 1 hard lock / Block 0 SoftLock, SoftLock on both
blocks, and hard lock on both blocks. Locking both blocks is the same as Level 2, Block 1 except read
operation isn’t available. The fourth level of security is the most secure level. It doesn’t allow read/pro-
gram of internal memory or boot from external memory. For details on how to program the security lock
bits refer to the external host mode and in-application programming sections.
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