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參數(shù)資料
| 型號： | SST89V58RD2-33-I-NJE |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 70/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 40KB FLASH 44PLCC |
| 標準包裝： | 27 |
| 系列： | FlashFlex® |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，WDT |
| 輸入/輸出數(shù)： | 36 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 8K x 8 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
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2011 Silicon Storage Technology, Inc.
DS25087A
10/11
72
FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Not Recommended for New Designs
A Microchip Technology Company
Power-Saving Modes
The device provides two power saving modes of operation for applications where power consumption
is critical. The two modes are idle and power-down, see Table 27.
Idle Mode
Idle mode is entered setting the IDL bit in the PCON register. In idle mode, the program counter (PC) is
stopped. The system clock continues to run and all interrupts and peripherals remain active. The on-
chip RAM and the special function registers hold their data during this mode.
The device exits idle mode through either a system interrupt or a hardware reset. Exiting idle mode via
system interrupt, the start of the interrupt clears the IDL bit and exits idle mode. After exit the Interrupt
Service Routine, the interrupted program resumes execution beginning at the instruction immediately
following the instruction which invoked the idle mode. A hardware reset starts the device similar to a
power-on reset.
Power-down Mode
The power-down mode is entered by setting the PD bit in the PCON register. In the power-down mode,
the clock is stopped and external interrupts are active for level sensitive interrupts only. SRAM contents
are retained during power-down, the minimum VDD level is 2.0V.
The device exits power-down mode through either an enabled external level sensitive interrupt or a hard-
ware reset. The start of the interrupt clears the PD bit and exits power-down. Holding the external interrupt
pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high
to complete the exit. Upon interrupt signal being restored to logic VIH, the first instruction of the interrupt ser-
vice routine will execute. A hardware reset starts the device similar to power-on reset.
To exit properly out of power-down, the reset or external interrupt should not be executed before the
VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage long enough at its nor-
mal operating level for the oscillator to restart and stabilize (normally less than 10 ms).
Table 27: Power Saving Modes
Mode
Initiated by
State of MCU
Exited by
Idle Mode
Software
(Set IDL bit in
PCON) MOV
PCON, #01H;
CLK is running.
Interrupts, serial port and
timers/counters are active.
Program Counter is
stopped. ALE and PSEN#
signals at a HIGH level
during Idle. All registers
remain unchanged.
Enabled interrupt or hardware reset. Start of interrupt
clears IDL bit and exits idle mode, after the ISR RETI
instruction, program resumes execution beginning at
the instruction following the one that invoked idle
mode. A user could consider placing two or three
NOP instructions after the instruction that invokes idle
mode to eliminate any problems. A hardware reset
restarts the device similar to a power-on reset.
Power-
down
Mode
Software
(Set PD bit in
PCON)
MOV PCON,
#02H;
CLK is stopped. On-chip
SRAM and SFR data is
maintained. ALE and
PSEN# signals at a LOW
level during power -down.
External Interrupts are
only active for level sensi-
tive interrupts, if enabled.
Enabled external level sensitive interrupt or hardware
reset. Start of interrupt clears PD bit and exits power-
down mode, after the ISR RETI instruction program
resumes execution beginning at the instruction follow-
ing the one that invoked power-down mode. A user
could consider placing two or three NOP instructions
after the instruction that invokes power-down mode to
eliminate any problems. A hardware reset restarts the
device similar to a power-on reset.
T0-0.0 25087
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SST89V58RD2-33-I-NJE1 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89V58RD2-33-I-NJF2 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89V58RD2-33-I-PI | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89V58RD2-33-I-PIE1 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89V58RD2-33-I-PIF2 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
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