參數(shù)資料
型號: SST89V58RD2-33-I-NJE
廠商: Microchip Technology
文件頁數(shù): 67/92頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 40KB FLASH 44PLCC
標(biāo)準(zhǔn)包裝: 27
系列: FlashFlex®
核心處理器: 8051
芯體尺寸: 8-位
速度: 33MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 8K x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
2011 Silicon Storage Technology, Inc.
DS25087A
10/11
7
FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Not Recommended for New Designs
A Microchip Technology Company
P3[1]
O
TXD: UART - Transmit output
P3[2]
I
INT0#: External Interrupt 0 Input
P3[3]
I
INT1#: External Interrupt 1 Input
P3[4]
I
T0: External count input to Timer/Counter 0
P3[5]
I
T1: External count input to Timer/Counter 1
P3[6]
O
WR#: External Data Memory Write strobe
P3[7]
O
RD#: External Data Memory Read strobe
PSEN#
I/O
Program Store Enable: PSEN# is the Read strobe to External Program Store.
When the device is executing from Internal Program Memory, PSEN# is inactive
(VOH). When the device is executing code from External Program Memory, PSEN#
is activated twice each machine cycle, except when access to External Data Mem-
ory while one PSEN# activation is skipped in each machine cycle. A forced high-to-
low input transition on the PSEN# pin while the RST input is continually held high for
more than 20 machine cycles will cause the device to enter External Host mode for
programming.
RST
I
Reset: While the oscillator is running, a high logic state on this pin for two machine
cycles will reset the device. After a reset, if the PSEN# pin is driven by a high-to-low
input transition while the RST input pin is held high, the device will enter the External
Host mode, otherwise the device will enter the Normal operation mode.
EA#
I
External Access Enable: EA# must be driven to VIL in order to enable the device to
fetch code from the External Program Memory. EA# must be driven to VIH for inter-
nal program execution. However, Security lock level 4 will disable EA#, and program
execution is only possible from internal program memory. The EA# pin can tolerate a
high voltage2 of 12V.
ALE/
PROG#
I/O
Address Latch Enable: ALE is the output signal for latching the low byte of the
address during an access to external memory. This pin is also the programming
pulse input (PROG#) for flash programming. Normally the ALE3 is emitted at a con-
stant rate of 1/6 the crystal frequency4 and can be used for external timing and
clocking. One ALE pulse is skipped during each access to external data memory.
However, if AO is set to 1, ALE is disabled.
P4[3:0]5
I/O with
internal
pull-ups
Port 4: Port 4 is an 4-bit bi-directional I/O port with internal pull-ups. The port 4 output
buffers can drive LS TTL inputs. Port 4 pins are pulled high by the internal pull-ups when
‘1’s are written to them and can be used as inputs in this state. As inputs, port 4 pins that
are externally pulled low will source current because of the internal pull-ups.
P4[0]
I/O
Bit 0 of port 4
P4[1]
I/O
Bit 1 of port 4
P4[2] /
INT3#
I/O
Bit 2 of port 4 / INT3# External interrupt 3 input
P4[3] /
INT2#
I/O
Bit 3 of port 4 / INT2# External interrupt 2 input
XTAL1
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
XTAL2
O
Crystal 2: Output from the inverting oscillator amplifier
VDD
I
Power Supply
VSS
I
Ground
T0-0.0 25087
1. I = Input; O = Output
2. It is not necessary to receive a 12V programming supply voltage during flash programming.
Table 1: Pin Descriptions (Continued) (2 of 2)
Symbol
Type1
Name and Functions
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