REV. 5.0.3 2.17 Sleep Mode & Wake-up Indicator The 650A is designed to oper" />
參數(shù)資料
型號: ST16C650ACJ44TR-F
廠商: Exar Corporation
文件頁數(shù): 13/50頁
文件大?。?/td> 0K
描述: IC UART FIFO 32B 44PLCC
標(biāo)準(zhǔn)包裝: 500
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 32 字節(jié)
規(guī)程: 打印機(jī),RS232,RS422,RS485
電源電壓: 2.9 V ~ 5.5 V
帶并行端口:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
ST16C650A
20
2.90V TO 5.5V UART WITH 32-BYTE FIFO
REV. 5.0.3
2.17
Sleep Mode & Wake-up Indicator
The 650A is designed to operate with low power consumption. A special sleep mode is included to further
reduce power consumption when the chip is not being used. All of these conditions must be satisfied for the
650A to enter sleep mode:
no interrupts pending 650A (ISR bit-0 = 1)
sleep mode is enabled (IER bit-4 = 1)
modem inputs are not toggling (MSR bits 0-3 = 0)
RX input pin is idling at a logic 1
The 650A stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for
no clock output as an indication that the device has entered the sleep mode.
The 650A resumes normal operation by any of the following:
a receive data start bit transition (logic 1 to 0)
a data byte is loaded to the transmitter, THR or FIFO
a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the sleep mode is enabled and the 650A is awakened by one of the conditions described above, an interrupt
is issued by the 650A to signal to the CPU that it is awake. The lower nibble of the interrupt source register
(ISR) will read a value of 0x1 for this interrupt and reading the ISR clears this interrupt. Since the same value
(0x1) is also used to indicate no pending interrupt, users should exercise caution while using the sleep mode.
Once awakened, the 650A will return to the sleep mode automatically after any other interrupting condition (the
true cause of waking up the 650A) has been serviced. If the 650A is awakened by the modem inputs, a read to
the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an
interrupt is pending. The 650A will stay in the sleep mode of operation until it is disabled by setting IER bit-4 to
a logic 0.
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