REV. 5.0.3 2.90V TO 5.5V UART WITH 32-BYTE FIFO 2.1.1 PC MODE The PC mode interface includes an on-chip address decoder and interru" />
參數(shù)資料
型號(hào)： ST16C650ACJ44TR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 50/50頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 32B 44PLCC
標(biāo)準(zhǔn)包裝： 500
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 32 字節(jié)
規(guī)程： 打印機(jī)，RS232，RS422，RS485
電源電壓： 2.9 V ~ 5.5 V
帶并行端口： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
ST16C650A
9
REV. 5.0.3
2.90V TO 5.5V UART WITH 32-BYTE FIFO
2.1.1
PC MODE
The PC mode interface includes an on-chip address decoder and interrupt selection function for the standard
PC COM 1-4 port addresses. The selection is made through three input signals: S1, S2 and S3. The selection
summary is shown in Table 1. Although the on-chip address decoder was designed for PC applications
ranging from 0x278 to 0x3FF, it can fit into an embedded applications by offsetting the address lines to the
650A. An example is shown in Figure 5 where the UART is operating from 0x80F8 to 0x80FF address space.
Operating in the PC mode eliminates external address decode components.
TABLE 1: PC MODE INTERFACE ON-CHIP ADDRESS DECODER AND INTERRUPT SELECTION.
SEL INPUT
INPUTS
A9-A3 ADDRESS LINES TO
ON-CHIP DECODER
COM/LPT PORT
SELECTION
IRQ OUTPUT SELECTION
0
0 0 0
0x3F8 - 0x3FF
COM-1
IRQB (for PC’s IRQ4)
0
0 0 1
0x2F8 - 0x2FF
COM-2
IRQC (for PC’s IRQ3)
0
0 1 0
0x3E8 - 0x3EF
COM-3
IRQB (for PC’s IRQ4)
0
0 1 1
0x2E8 - 0x2EF
COM-4
IRQC (for PC’s IRQ3)
0
1 0 0
0x3F8 - 0x3FF
COM-1
IRQA (for PC’s IRQn)
0
1 0 1
0x2F8 - 0x2FF
COM-2
IRQA (for PC’s IRQn)
0
1 1 0
0x3E8 - 0x3EF
COM-3
IRQA (for PC’s IRQn)
0
1 1 1
0x2E8 - 0x2EF
COM-4
IRQA (for PC’s IRQn)
0
- - -
0x278 - 0x27F
LPT-2
N/A
0
- - -
0x378 - 0x37F
LPT-1
N/A
FIGURE 5. PC MODE INTERFACE IN AN EMBEDDED APPLICATION.
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A14
A15
AE N #
IO W #
IO R #
RE S E T
D0
D1
D2
D3
D4
D5
D6
D7
IO W #
A0
A1
A2
R E SET
VC C
IN T
IR Q A
SE L
VC C
GN D
IO R #
IR Q B
IR Q C
A3
A4
A5
A6
A7
A8
A9
AEN *
OP 1 #
RI#
CD#
DS R#
CT S #
RX
TX
RT S #
DT R#
S1
S2
S3
VCC
GN D
E m bedded A pplication set to operate
at address 0x80F 8 to 0x80F F
S3, S2, S1
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