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參數(shù)資料
| 型號： | ST16C650ACJ44TR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 8/50頁 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 32B 44PLCC |
| 標準包裝： | 500 |
| 特點： | * |
| 通道數(shù)： | 1，UART |
| FIFO's： | 32 字節(jié) |
| 規(guī)程： | 打印機，RS232，RS422，RS485 |
| 電源電壓： | 2.9 V ~ 5.5 V |
| 帶并行端口： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應商設備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
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FIGURE 11. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X Clock
E
rror
Tags
(32-sets
)
E
rror
T
ags
in
LS
R
bi
ts
4:2
32 bytes by 11-bit
wide FIFO
Receive Data Characters
FIFO
Trigger=16
Example
:
- RX FIFO trigger level selected at 16 bytes
Data fills to
24
Data falls to
8
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
ST16C650A
16
2.90V TO 5.5V UART WITH 32-BYTE FIFO
REV. 5.0.3
2.11
Automatic RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 12):
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS output pin (MCR bit-1 to logic 1 after it is enabled).
With the Auto RTS function enabled, the RTS# output pin will not be de-asserted (logic 1) when the receive
FIFO reaches the programmed trigger level, but will be de-asserted when the FIFO reaches the next trigger
level (See Table 10). The RTS# output pin will be asserted again after the FIFO is unloaded to the next trigger
level below the programmed trigger level. However, even under these conditions, the 650A will continue to
accept data until the receive FIFO is full if the remote UART transmitter continues to send data.
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin is de-asserted (logic 1) during Auto RTS flow control mode: ISR bit-5 will be set to logic 1.
2.12
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 12):
Enable auto CTS flow control using EFR bit-7.
With the Auto CTS function enabled, the UART will suspend transmission as soon as the stop bit of the
character in the Transmit Shift Register has been shifted out. Transmission is resumed after the CTS# input is
re-asserted (logic 0), indicating more data may be sent.
Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (logic 1) during Auto CTS flow control mode: ISR bit-5 will be set to 1.
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| ST16C650ACP40 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.90V TO 5.5V UART WITH 32-BYTE FIFO |
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| ST16C650ACQ48-F | 功能描述:UART 接口集成電路 UART W/32BYTEFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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