REV. 5.0.3 2.90V TO 5.5V UART WITH 32-BYTE FIFO 2.18 Internal Loopback The 650A UART provides an internal loopback c" />
參數(shù)資料
型號: ST16C650AIQ48-F
廠商: Exar Corporation
文件頁數(shù): 14/50頁
文件大小: 0K
描述: IC UART FIFO 32B 48TQFP
標(biāo)準(zhǔn)包裝: 250
特點: *
通道數(shù): 1,UART
FIFO's: 32 字節(jié)
規(guī)程: 打印機,RS232,RS422,RS485
電源電壓: 2.9 V ~ 5.5 V
帶并行端口:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
ST16C650A
21
REV. 5.0.3
2.90V TO 5.5V UART WITH 32-BYTE FIFO
2.18
Internal Loopback
The 650A UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 14 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal. Also, Auto
RTS/CTS is not supported during internal loopback.
FIGURE 14. INTERNAL LOOP BACK
TX
RX
M
odem
/
G
eneral
Purpos
e
C
o
ntrol
Logic
Intern
al
Data
B
u
s
Lin
es
and
C
o
n
tr
o
lSignals
RTS#
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTS#
DTR#
DSR#
RI#
CD#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
OP2#
VCC
OP1#
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