參數(shù)資料
型號: ST20GP6
英文描述: MAX 7000 CPLD 256 MC 208-RQFP
中文描述: GPS處理器
文件頁數(shù): 50/116頁
文件大?。?/td> 1107K
代理商: ST20GP6
ST20-GP1
50/116
9
Programmable memory interface
The ST20-GP1 programmable memory interface provides glueless support for up to four banks of
SRAM or ROM memory. Sufficient configuration options are provided to enable the interface to be
used with a wide variety of SRAM speeds, permitting systems to be built with optimum price/
performance trade-offs.
Although designed primarily for SRAM-like memory devices, the configurability enables glueless
connection to other peripheral devices such as FIFOs and UARTs.
The programmable memory interface is also referred to as the external memory interface (EMI).
The EMI provides configuration information for four independent banks of external memory
devices. The addresses of these bank boundaries are hard wired to give each bank one quarter of
the address space of the machine. Bank 0 occupies the lowest quarter of the [signed] address
space, bank 3 is the highest, see Figure 9.1. Each bank can contain up to 1 Mbyte of external
memory.
Figure 9.1 Memory allocation
00000000
FFFFFFFF
7FFFFFFF
80000000
Internal SRAM
BFFFFFFF
C0000000
3FFFFFFF
40000000
On-chip peripheral registers (including the EMI
configuration registers) are mapped into the upper
half of this bank.
B
Addresses shown are physical addresses.
On-chip peripheral
registers
Subsystem
Traps/
Internal
20000000
1FFFFFFF
B
B
B
80000000
MemStart
80000FFF
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參數(shù)描述
ST20-GP6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR
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ST20GP6X33S 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR