參數(shù)資料
型號(hào): ST20GP6
英文描述: MAX 7000 CPLD 256 MC 208-RQFP
中文描述: GPS處理器
文件頁(yè)數(shù): 85/116頁(yè)
文件大?。?/td> 1107K
代理商: ST20GP6
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ST20-GP1
85/116
14 Parallel input/output
The ST20-GP1 device has 6 bits of Parallel Input/Output (PIO), each bit is programmable as an
input or an output.
The input bits can be compared against a register and an interrupt generated when the value is not
equal.
14.1 PIO Port
Each of the bits of the PIO port has a corresponding bit in the PIO registers associated with the
port. These registers hold: output data for the port (
POut
); the input data read from the pin (
PIn
);
PIO bit configuration register (
PC1
); and the two input compare function registers (
PComp
and
PMask
).
All of the registers, except the
PIn
register, are each mapped onto three separate addresses so
that bits can be set or cleared individually.
The
Set_
register allows bits to be set individually. Writing a ‘1’ in this register sets the
corresponding bit in the associated
register, a ‘0’ leaves the bit unchanged.
The
Clear_
register allows bits to be cleared individually. Writing a ‘1’ in this register resets the
corresponding bit in the associated register, a ‘0’ leaves the bit unchanged.
14.1.1 PIO Data registers
The base addresses for the PIO registers are given in the Memory Map chapter.
POut register
This register holds output data for the port.
POut
PIO port base address + #00
Read/Write
Bit
Bit field
Function
0
POut0
Output data bit 0
1
POut1
Output data bit 1
2
POut2
Output data bit 2
3
POut3
Output data bit 3
4
POut4
Output data bit 4
5
POut5
Output data bit 5
Table 14.1
POut
register format
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