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參數(shù)資料
| 型號： | ST62E94F1 |
| 英文描述： | IC PSRAM 32MB 54-VFBGA |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 30/82頁 |
| 文件大?。?/td> | 870K |
| 代理商： | ST62E94F1 |
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ST62T18C/E18C
INTERRUPTS
(Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h
—
Write Only
Reset status: 00h
Bit 7, Bits 3-0 =
Unused
.
Bit 6 =
LES
:
Level/Edge Selection bit
.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 =
ESB
:
Edge Selection bit
.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 =
GEN
:
Global Enable Interrupt
. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Interrupt sources available on the ST62E18C/
T18C are summarized in the
Table 10
with associ-
ated mask bit to enable/disable the interrupt re-
quest.
Table 10. Interrupt Requests and Mask Bits
7
0
-
LES
ESB
GEN
-
-
-
-
Peripheral
Register
Address
Register
C8h
D4h
D1h
Mask bit
Masked Interrupt Source
Interrupt
source
All
source 4
source 4
GENERAL
TIMER
A/D CONVERTER
IOR
TSCR1
ADCR
GEN
ETI
EAI
RXIEN
TXIEN
OVIE
CPIE
EIE
ALL
ORPAn-DRPAn
ORPBn-DRPBn
ORPDn-DRPDn
All Interrupts, excluding NM
I
TMZ: TIMER Overflow
EOC: End of Conversion
RXRDY: Byte received
TXMT: Byte sent
OVF: ARTIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin
End of Transmission
PAn pin
PBn pin
PDn pin
UART
UARTCR
D7h
source 4
ARTIMER
ARMC
E5h
source 3
SPI
Port PAn
Port PBn
Port PDn
SIDR
ORPA-DRPA
ORPB-DRPB
ORPD-DRPD
DCh
C0h-C4h
C1h-C5h
C3h-C7h
source 1
source 1
source 2
source 2
30
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