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| 型號： | ST62E94F1 |
| 英文描述： | IC PSRAM 32MB 54-VFBGA |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 36/82頁 |
| 文件大?。?/td> | 870K |
| 代理商： | ST62E94F1 |
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ST62T18C/E18C
I/O PORTS
(Cont’d)
4.1.1 Operating Modes
Each pin may be individually programmed as input
or output with various configurations.
This is achieved by writing the relevant bit in the
Data (DR), Data Direction (DDR) and Option reg-
isters (OR).
Table 1
illustrates the various port
configurations which can be selected by user soft-
ware.
4.1.1.1 Input Options
Pull-up, High Impedance Option. All input lines
can be individually programmed with or without an
internal pull-up by programming the OR and DR
registers accordingly. If the pull-up option is not
selected, the input pin will be in the high-imped-
ance state.
4.1.1.2 Interrupt Options
All input lines can be individually connected by
software to the interrupt system by programming
the OR and DR registers accordingly. The inter-
rupt trigger modes (falling edge, rising edge and
low level) can be configured by software as de-
scribed in the Interrupt Chapter for each port.
4.1.1.3 Analog Input Options
Some pins can be configured as analog inputs by
programming the OR and DR registers according-
ly. These analog inputs are connected to the on-
chip 8-bit Analog to Digital Converter.
ONLY ONE
pin should be programmed as an analog input at
any time, since by selecting more than one input
simultaneously their pins will be effectively short-
ed.
Table 12. I/O Port Option Selection
Note:
X = Don’t care
DDR
0
0
0
0
1
1
OR
0
0
1
1
0
1
DR
0
1
0
1
X
X
Mode
Input
Input
Input
Input
Output
Output
Option
With pull-up, no interrupt
No pull-up, no interrupt
With pull-up and with interrupt
Analog input (when available)
Open-drain output (20mA sink when available)
Push-pull output (20mA sink when available)
36
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