參數(shù)資料
型號(hào)： ST7285C
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
中文描述： 8位微控制器48,000鐵路發(fā)展策略光盤，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口
文件頁數(shù)： 31/117頁
文件大小： 748K
代理商： ST7285C
31/117
ST7285C
SERIAL COMMUNICATIONS INTERFACE
(Cont’d)
The TC bit is automatically set to “1” when trans-
mission of a frame containing Data, a Preamble or
a Break is complete, if:
– TE = ”1”, TDRE = ”1”, no word is currently being
transmitted and no preamble or BREAK is await-
ing transmission.
– TE = ”0” and the current word or preamble or
BREAK has been transmitted
The TC bit is a flag indicating that one of the above
sequences has occurred. This bit is reset to “0” by
an access to the SCSR followed by a write opera-
tion into the data register or when TDREis reset to
“0”. Transmitter operation is in no way modified by
the status of this bit.
Bit-5 =
RDRF
Received Data Ready Flag
This bit, when set to “1”, indicates that the content
of the RDR has been transferred into the SCDR. If
a Frame Error or Noise has been detected during
reception, the corresponding flags will be set.
The RDRF bit is reset to “0” by an access to the
SCSR followed by a data register read operation.
Bit-4 =
IDLE
Idle Line Detect
When the idle line detect bit is set it indicates that
the receiver idle line is detected (receipt of a mini-
mum number of ones (10 when M=0, 11 when
M=1) to constitute the number of bits in the frame
format. This allows a receiver that is not in the
wake-up mode to detect the end of a message or
the preamble of a new message or to re-synchro-
nize with the transmitter. The IDLE bitis cleared by
accessing the SCSR (with idle set) followed by a
read of the data register. The IDLE bit will not be
set again until the RDRF bit has been setitself (i.e.
a new idle line occurs). The IDLE bit is not set by
an idle line when the receiver wakes up from wake
up mode.
Bit-3 =
OR
Overrun Error
This bit is set to “1”, when the word currently being
received in the shift register is ready to be trans-
ferred into the data register while the latter is al-
ready full (RDRF=”1”). All transfers will remain dis-
abled as long as RDRF remains at “1”. Data regis-
ter content will not be lost but the shift register will
be overwritten. The OR bit is reset by an access to
the SCSR followed by a data register read opera-
tion.
Bit-2 =
NF
Noise Flag
This bit is set to “1” when noise is detected on an
acknowledge START bit or a data bit or a stop bit.
The NF is set to “1” when the noise is detected at
the rising edge of RDRF and is representative of
the word present in the data register. This bit does
not generate interrupts as it appears at the same
time as RDRF which itself generates an interrupt.
The NF bit is set to “0” by a SCSR read operation
followed by a data register read operation.
Bit-1 =
FE
Framing Error
This bit is set to “1” when the STOP bit is not rec-
ognized on reception at the expected moment, fol-
lowing either a de-synchronization,
noise or when a BREAk is received. The word will,
however still be transferred to the data register. As
in the case of the NF bit,the FEW bit does not gen-
erate an interrupt as it appears at the same time as
RDRF bit. If the word currently being transferred
causes both frame error and reception overspeed,
it will be transferred and only the OR bit will be set
to “1”. The FE bit is reset to “0” by a SCSR read
operation followed by a data register read opera-
tion.
Bit-0 = Unused
4.2.7.5 Baud Rate Register (SCBRR)
Address: 0052h
—
Read/Write
Reset Value: 00X----Xb
Contains two bits for selection of the first prescaler
factor, three bits for selection of the transmitter
rate divisor and three bits for the receiver rate divi-
sor.
excessive
Bit-7 =
SCP1
First prescaler MSB
Bit-6 =
SCP0
First prescaler LSB
These 2 prescaling bits allow several standard
clock division ranges:
Bit-5 =
SCT2
Transmitter rate divisor MSB
Bit-4 =
SCT1
Transmitter rate divisor NSB
Bit-3 =
SCT0
Transmitter rate divisor LSB
These 3 bits, in conjunction with the 2 previous bits
define the total division applied to the bus clock to
yield the transmit rate clock in conventional Baud
Rate Generator mode.
7
6
5
4
3
2
1
0
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
SCP1
0
0
1
1
SCP0
0
1
0
1
PR Prescaling factor
1
3
4
13
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