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參數(shù)資料
| 型號： | ST72P621J4B1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 62/136頁 |
| 文件大?。?/td> | 2475K |
| 代理商： | ST72P621J4B1 |
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ST7262
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9 I/O PORTS
9.1 INTRODUCTION
The I/O ports offer different functional modes:
transfer of data through digital inputs and outputs
and for specific pins:
– Analog signal input (ADC)
– Alternate signal input/output for the on-chip pe-
ripherals.
– External interrupt generation
An I/O port is composed of up to 8 pins. Each pin
can be programmed independently as digital input
or digital output.
9.2 FUNCTIONAL DESCRIPTION
Each port is associated with 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
Each I/O pin may be programmed using the corre-
sponding register bits in DDR register: bit x corre-
sponding to pin x of the port. The same corre-
spondence is used for the DR register.
Table 8. I/O Pin Functions
9.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Notes:
1. All the inputs are triggered by a Schmitt trigger.
2. When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port is
configured as an output.
Interrupt function
When an external interrupt function of an I/O pin, is
enabled using the ITFRE registers, an event on
this I/O can generate an external Interrupt request
to the CPU. The interrupt sensitivity is programma-
ble, the options are given in the description of the
ITRFRE interrupt registers.
Each pin can independently generate an Interrupt
request.
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see Interrupts sec-
tion). If more than one input pin is selected simul-
taneously as interrupt source, this is logically AN-
Ded and inverted. For this reason, if an event oc-
curs on one of the interrupt pins, it masks the other
ones.
9.2.2 Output Mode
The pin is configured in output mode by setting the
corresponding DDR register bit (see Table 7).
In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.
Note: In this mode, the interrupt function is disa-
bled.
9.2.3 Alternate Functions
Digital Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).
When the signal is going to an on-chip peripheral,
the I/O pin has to be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
Notes:
1. Input pull-up configuration can cause an unex-
pected value at the alternate peripheral input.
2. When the on-chip peripheral uses a pin as input
and output, this pin must be configured as an
input (DDR = 0).
Warning: Alternate functions of peripherals must
must not be activated when the external interrupts
are enabled on the same pin, in order to avoid
generating spurious interrupts.
DDR
MODE
0
Input
1
Output
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