參數(shù)資料
型號： ST72P621J4B1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝： PLASTIC, SDIP-32
文件頁數(shù)： 76/136頁
文件大?。?/td> 2475K
代理商： ST72P621J4B1
ST7262
44/136
PWM AUTO-RELOAD TIMER (Cont’d)
Independent PWM signal generation
This mode allows up to two Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during HALT mode.
Each PWMx output signal can be selected inde-
pendently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as out-
put push-pull alternate function.
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARTARR register value.
fPWM = fCOUNTER / (256 - ARTARR)
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
OPx (output polarity) bit in the PWMCR register.
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARTARR reg-
ister.
The maximum available resolution for the PWMx
duty cycle is:
Resolution = 1 / (256 - ARTARR)
Note: To get the maximum resolution (1/256), the
ARTARR register must be 0. With this maximum
resolution, 0% and 100% can be obtained by
changing the polarity.
Figure 33. PWM Auto-reload Timer Function
DUTY CYCLE
REGISTER
AUTO-RELOAD
REGISTER
PW
M
x
O
U
T
P
U
T
t
255
000
WITH OEx=1
AND OPx=0
(ARTARR)
(PWMDCRx)
WITH OEx=1
AND OPx=1
CO
UN
T
E
R
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