參數(shù)資料
型號: ST72P621J4B1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝: PLASTIC, SDIP-32
文件頁數(shù): 95/136頁
文件大?。?/td> 2475K
代理商: ST72P621J4B1
ST7262
61/136
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.5.4 Single Master System
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 45).
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Figure 45. Single Master / Multiple Slave Configuration
MISO
MOSI
MISO
SS
SCK
5V
Ports
Slave
MCU
Slave
MCU
Slave
MCU
Slave
MCU
Master
MCU
相關(guān)PDF資料
PDF描述
ST72P621J4T1 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO34
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