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參數(shù)資料
| 型號(hào)： | ST72T774S9T1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | TQFP-44 |
| 文件頁(yè)數(shù)： | 115/144頁(yè) |
| 文件大?。?/td> | 1280K |
| 代理商： | ST72T774S9T1 |
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ST72774/ST727754/ST72734
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SYNC PROCESSOR (SYNC) (Cont’d)
HORIZONTAL SYNC GENERATOR REGISTER
(HGENR)
Read/Write
Reset Value: 0000 0000 (00h)
Case HVGEN = 1: Generation mode
In this mode, this register contains the Hsync free-
running frequency.
The generated signal is:
- Pulse width: 2 s.
- Period PH = ((HGENR+1)/4) s.
- Polarity: Positive
Note: The value in HGENR must be in the range [8..255]
.
Case HVGEN = 0: Analyzer/corrector Mode
Sub-case HACQ = 1: Analyzer Mode
By setting HACQ bit by software the Analyzer
mode starts. When HACQ is cleared by hardware,
HGENR
returns
the
duration
of
HSYNCO/
HFBACK low level. The analysis should be done
before corrector mode.
Sub-case HACQ = 0: Corrector Mode
In this mode, the final HSYNCO signal on the pin
can be corrected in order to detect and inhibit pre/
post equalization pulses.
VERTICAL
SYNC
GENERATOR
REGISTER
(VGENR)
Read/Write
Reset Value: 0000 0000 (00h)
Case HVGEN = 1: Generation mode
In this mode, this register contains the Vsync free-
running frequency (11-bit value).
The generated signal is:
- Pulse width: 4 * PH s (horizontal period).
- Period PV = PH * (V11bits) s.
- Polarity: Positive
Note: The value in VGENR must be in the range [5..255]
The Vsync generation mode works as an 11-bit hor-
izontal line counter (2047 scan lines per frame
max.). The 3 LSB are in the CFGR register. Refer
to Figure 44.
Case HVGEN = 0: Analyzer/Corrector Mode
Sub-case VACQ = 1: Analyzer Mode
Set the VACQ bit to start analyzer mode. When
VACQ is cleared by hardware, VGENR/CFGR
returns the number of scan lines during the
VSYNCO/VFBACK low level period.
Sub-case VACQ = 0: Corrector Mode
VSYNCO pulse width is extended by VGENR scan
lines. If VGENR = 0, all VSYNCO corrections are
disabled.
70
MSB
LSB
70
MSB
LSB
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