參數(shù)資料
型號: ST72T774S9T1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP44
封裝: TQFP-44
文件頁數(shù): 80/144頁
文件大小: 1280K
代理商: ST72T774S9T1
ST72774/ST727754/ST72734
40/144
Table 13. Watchdog Timing (fCPU = 8 MHz)
Notes:
Following a reset, the watchdog is
disabled. Once activated it cannot be disabled,
except by a reset.
The T6 bit can be used to generate a software
reset (the WDGA bit is set and the T6 bit is
cleared).
4.2.4 Interrupts
None.
4.2.5 Register Description
CONTROL REGISTER (CR)
Read /Write
Reset Value: 0111 1111 (7F h)
Bit 7 = WDGA
Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bit 6:0 = T[6:0]
7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
Table 14. Watchdog Timer Register Map and Reset Values
CR Register
initial value
WDG timeout period
(ms)
Max
FFh
393.216
Min
C0h
6.144
70
WDGA
T6
T5
T4
T3
T2
T1
T0
Address
(Hex.)
Register
Label
76
5
4
32
10
08
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
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