參數(shù)資料
型號(hào)： ST92195C8T1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP64
封裝： TQFP-64
文件頁(yè)數(shù)： 192/250頁(yè)
文件大?。?/td> 3010K
代理商： ST92195C8T1/XXX
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ST92195 ST92T195 ST92E195 - INTERRUPTS
PRIORITY LEVEL ARBITRATION (Cont’d)
3.4.3 Simultaneous Interrupts
If two or more requests occur at the same time and
at the same priority level, an on-chip daisy chain,
specific to every ST9 version, selects the channel
with the highest position in the chain, as shown in
Table 7. on page 46
Table 7. Daisy Chain Priority for the ST92195C/D
3.4.4 Dynamic Priority Level Modification
The main program and routines can be specifically
prioritized. Since the CPL is represented by 3 bits
in a read/write register, it is possible to modify dy-
namically the current priority value during program
execution. This means that a critical section can
have a higher priority with respect to other inter-
rupt requests. Furthermore it is possible to priori-
tize even the Main Program execution by modify-
ing the CPL during its execution. See Figure 20 on
page 46
Figure 20. Example of Dynamic priority
level modification in Nested Mode
3.5 ARBITRATION MODES
The ST9 provides two interrupt arbitration modes:
Concurrent mode and Nested mode. Concurrent
mode is the standard interrupt arbitration mode.
Nested mode improves the effective interrupt re-
sponse time when service routine nesting is re-
quired, depending on the request priority levels.
The IAM control bit in the CICR Register selects
Concurrent Arbitration mode or Nested Arbitration
Mode.
3.5.1 Concurrent Mode
This mode is selected when the IAM bit is cleared
(reset condition). The arbitration phase, performed
during every instruction, selects the request with
the highest priority level. The CPL value is not
modified in this mode.
Start of Interrupt Routine
The interrupt cycle performs the following steps:
– All maskable interrupt requests are disabled by
clearing CICR.IEN.
– The PC low byte is pushed onto system stack.
– The PC high byte is pushed onto system stack.
– If ENCSR is set, CSR is pushed onto system
stack.
– The Flag register is pushed onto system stack.
– The PC is loaded with the 16-bit vector stored in
the Vector Table, pointed to by the IVR.
– If ENCSR is set, CSR is loaded with ISR con-
tents; otherwise ISR is used in place of CSR until
iret
instruction.
End of Interrupt Routine
The Interrupt Service Routine must be ended with
the iret instruction. The iret instruction exe-
cutes the following operations:
– The Flag register is popped from system stack.
– If ENCSR is set, CSR is popped from system
stack.
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
– All unmasked Interrupts are enabled by setting
the CICR.IEN bit.
– If ENCSR is reset, CSR is used instead of ISR.
Normal program execution thus resumes at the in-
terrupted instruction. All pending interrupts remain
pending until the next ei instruction (even if it is
executed during the interrupt service routine).
Note: In Concurrent mode, the source priority level
is only useful during the arbitration phase, where it
is compared with all other priority levels and with
the CPL. No trace is kept of its value during the
ISR. If other requests are issued during the inter-
rupt service routine, once the global CICR.IEN is
re-enabled, they will be acknowledged regardless
of the interrupt service routine’s priority. This may
cause undesirable interrupt response sequences.
Highest Position
Lowest Position
INTA0
INTA1
INTB0
INTB1
INTC0
INTC1
INTD0
INTD1
INT0/WDT
Standard Timer 0
INT2/SPI
AD Converter/IC
INT4/SYNC (EOFVBI)
INT5/SYNC (FLDST)
INT6/Standard Timer 1
INT7
6
5
4
7
Priority Level
MAIN
CPL is set to 5
CPL=7
MAIN
INT 6
CPL=6
INT6
ei
CPL is set to 7
CPL6 > CPL5:
INT6 pending
INTERRUPT 6 HAS PRIORITY LEVEL 6
by MAIN program
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