- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98147 > ST92195C8T1/XXX (STMICROELECTRONICS) 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號(hào)： | ST92195C8T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁(yè)數(shù)： | 241/250頁(yè) |
| 文件大小： | 3010K |
| 代理商： | ST92195C8T1/XXX |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)當(dāng)前第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)
90/249
ST92195 ST92T195 ST92E195 - TELETEXT DISPLAY STORAGE RAM INTERFACE
TDSRAM (Cont’d)
7.3.3 Initialisation
7.3.3.1 Clock Initialisation
Before initialising the TRI, first initialise the pixel
clock. Refer to the Application Examples in the
OSD chapter and to the RCCU chapter for a de-
scription of the clock control registers.
7.3.3.2 TRI Initialisation
It is recommended to wait for a stable clock issued
from the Pixel frequency multiplier before enabling
the TDSRAM interface.
Use the CONFIG register to initialise and start
the TRI and Acquisition units. Note: The AON and
DON bits can only be changed while GEN=0
Example:
spp #0x26
ld config, #0x06 ; AON,DON,GEN=0
or config, #0x01 ; set GEN=1
During and after a reset, the TDSRAM interface is
forced into its "disable" mode where the sequencer
is forced into its idle state.
7.3.3.3 Multi-Byte Transfer (MBT) Initialisation
A multi-byte transfer corresponds to a 40-byte ex-
change between the RAM and an internal 40-byte
buffer located into the TDSRAM interface. This
buffer is register-mapped and can be directly ac-
cessed by the CPU in its register page space.
Start the MBT transfer by setting the BUSY bit in
the BUFC register.
Example:
spp #0x26
ld BUFC, #0x01 ;
;Start DMA transfer
;Poll on Busy bit
The exchange can be either a read (extraction of
40 consecutive bytes from the RAM starting at a
software programmed address) or a write (writing
of 40 consecutive bytes to the RAM starting at a
software programmed address). The address is a
13 bit-long word allowing access to any TDSRAM
location. The address can be either incremented
or decremented depending on a control bit.
While the transfer is running, the buffer is no long-
er software accessible ("busy bit" (BUFC.0) is set
to 1). Once the exchange is completed, this bit is
automatically reset and the MBT slots are auto-
matically given back to the CPU.
Four powerful data exchange modes are provided:
– Read only (transfer from the RAM to the buffer)
– Write only (transfer from the buffer to the RAM)
– Write with parity reject (if the byte presents a par-
ity error, it will not be written into the TDSRAM;
the corresponding location keeps its previous
content).
– Parity cancelled on write (the MSB is replaced by
"0" when the byte is written into the TDSRAM).
The "parity reject" and "parity cancelled" modes
can be used simultaneously during a write opera-
tion. In this case, the parity check will be done first
and the parity bit will be removed, if the write oper-
ation has to be performed. The parity check per-
formed is the following:
– The parity is correct when the number of 1s (cur-
rent byte) is an odd number.
– The parity is incorrect when the number of 1s
(current byte) is an even number.
A parity check flag (BUFC.5) is provided for the
whole buffer. This bit is set when a parity error is
detected during the write operation. This bit has to
be reset by software before starting another MBT.
7.3.3.4 100/120 Hz Applications
In 100/120 Hz applications, both the vertical and
horizontal beam scanning speeds are doubled
while the CVBS signal remains unchanged. To
handle this, the EOFVBI interrupt can be delayed
from the beginning of deflection line 25 to the be-
ginning of line 50 by setting the DS bit of the CON-
FIG register. If the DS bit is set, the interrupt is only
generated when the complete Teletext data is fully
sliced and stored.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST92195C6B1/XXX | 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PDIP56 |
| ST92195C4B1/XXX | 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PDIP56 |
| ST9291N3 | 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP56 |
| ST9291N6 | 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP56 |
| ST92E141K4D1 | 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST92195C9 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER |
| ST92195C9B1 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER |
| ST92195C9T1 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER |
| ST92195D | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER |
| ST92195D5 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。