參數(shù)資料
型號(hào)： ST92195C8T1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP64
封裝： TQFP-64
文件頁(yè)數(shù)： 82/250頁(yè)
文件大?。?/td> 3010K
代理商： ST92195C8T1/XXX
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ST92195 ST92T195 ST92E195 - VPS & WSS SLICER
VPS & WSS SLICER (Cont’d)
VPS/WSS CONTROL REGISTER (VPSWSSCR)
R249 - Read/Write
Register Page: 6
Reset value: 0000 0000 (00h)
Bit 7 = ENCELL:
VPS/WSS enable.
0 : WSS/VPS disabled (reset condition)
1 : WSS/VPS enabled
Bit 6 = VCRWIN: When this bit is set, the line se-
lect window for VPS becomes three lines wide (15-
17) while the line select for WSS becomes four
lines wide (21-24). The four lines are required due
to the uncertainty of the line number from a VCR
source and the repeated WSS signal found on
both lines 22 and 23.
When the bit is reset, VPS is active only on line 16
and WSS is active only on line 23.
Bit 5 = BIASWIN:
Bias Window is a control bit
used to keep the WSS and VPS bias window open
during the entire line. When set, the window is ac-
tive during the run-in and the data periods. This
feature may be used during poor signals or as a
backup due to leakage and noise problems on the
IC.
When reset, the window is defin
ed only for the run-in clock.
Bit 4 = VW_EN:
Clock Generating Unit Enable Bit
0: No clock is provided to the VPS/WSS slicer unit.
1: The VPS/WSS clock is provided by the Digital
Clock Generating Unit based on the 48.56 MHz
issued by the TXT frequency multiplier.
Note: This bit is valid only when the SLIEN bit of
the SLCCR register is set (refer to the Timing and
Clock Controller Chapter), i.e. when the PLL is en-
abled.
Bit 3 = WINDLY:
Window Delay Bit
This bit is common to VPS and WSS. Due to the
large range of signals in VPS mode (data start be-
tween 11ms and 14ms) the window which allows
to adjust the slicing level during the run-in clock
cannot be the same for early and late signals. This
bit has to be controlled to get a proper bias window
in VPS.
0: Run-in bias window defined for standard & too
late data (VPS data start between 12.35ms and
14ms).
1: Run-in bias window defined for too early data
(VPS data start between 11ms and 12.65ms)
Note: This bit has no influence on WSS bias win-
dow.
Bit 2:0 Reserved bits.
DUPLICATE WSS STATUS AND DATA REGIS-
TER (WSSDS3R)
R250 - Read Only/Reset by writing
Register Page: 6
Reset value: 0000 0000 (00h)
Bit 7 = Reserved.
Bit 6 = NWDATWS2:
New data in all three data
registers. Data will be written into this register with
or without bi-phase errors. The error bit for each
byte of data should be checked to validate any da-
ta. Reset by writing any value to this register or by
the leading edge of WSS Window, that initiates a
new acquisition.
Bit 5 = VFRMWSS2: Valid Framing code for WSS.
This bit is set when the framing code is error free.
Reset by the end of WSS window.
Bit 4 = GP1ERF2: This bit is set when any of the
Group 1 bits (WSS3-0) are received with a bi-
phase error.
Bit 3:0 = WSS2[3:0]: WSS Aspect Ratio Bits
70
EN-
CELL
VCRW
IN
BIAS-
WIN
VW_
EN
WIND-
LY
00
0
70
x
NWDAT
WS2
VFRMW
SS2
GP1ERF2- WSS2(3) WSS2(2) WSS2(1) WSS2(0)
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