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參數(shù)資料
| 型號(hào)： | T431616E-7S |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| 中文描述： | 100萬× 16內(nèi)存為512k × 16Bit的X 2Banks同步DRAM |
| 文件頁數(shù)： | 13/74頁 |
| 文件大?。?/td> | 781K |
| 代理商： | T431616E-7S |
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TE
CH
tm
T431616D/E
TM Technology Inc. reserves the right
P. 13
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode. Sequential
Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only supports burst length
of 4 and 8.
A3
0
1
Addressing Mode
Sequential
Interleave
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column address which
is input to the device. The internal column address is varied by the Burst Length as shown in the
following table. When the value of column address, (n + m), in the table is larger than 255, only
the least significant 8 bits are effective.
Data n
0
1
2
3
4
5
6
7
-
255
256
257
-
Column Address
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
-
n+255
n
n+1
-
2 words:
Burst Length
4 words:
8 words:
Full Page: Column address is repeated until terminated.
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address
bits in the sequence shown in the following table.
Data n
Data 0 A7 A6 A5 A4 A3 A2 A1 A0
Data 1 A7 A6 A5 A4 A3 A2 A1 A0#
Data 2 A7 A6 A5 A4 A3 A2 A1# A0
Data 3 A7 A6 A5 A4 A3 A2 A1# A0#
Data 4 A7 A6 A5 A4 A3 A2# A1 A0
Data 5 A7 A6 A5 A4 A3 A2# A1 A0#
Data 6 A7 A6 A5 A4 A3 A2# A1# A0
Data 7 A7 A6 A5 A4 A3 A2# A1# A0#
Column Address
Burst Length
4 words
8 words
CAS# Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The
minimum whole value satisfying the following formula must be programmed into this field.
t
CAC
(min)
≤
CAS# Latency X t
CK
A6
0
0
0
0
1
A5
0
0
1
1
X
A4
0
1
0
1
X
CAS# Latency
Reserved
1 clock
2 clocks
3 clocks
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T431616E-7SG | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| T436416A | 4M X 16 SDRAM |
| T436416A-10S | 4M X 16 SDRAM |
| T436416A-10SG | Terminal Block End Barrier; For Use With:AB1 Series Terminal Blocks; Accessory Type:End Barrier; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| T436416A-6S | 4M X 16 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T431616E-7SG | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
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| T4333 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIANGULAR TYPE |
| T43331G | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
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