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| 型號： | T431616E-7SG |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM |
| 中文描述： | 100萬× 16內(nèi)存為512k × 16Bit的X 2Banks同步DRAM |
| 文件頁數(shù)： | 10/74頁 |
| 文件大?。?/td> | 781K |
| 代理商： | T431616E-7SG |
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TE
CH
tm
T431616D/E
TM Technology Inc. reserves the right
P. 10
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
after the clock edge in which the last data-in element is registered. In order to avoid data contention, input data
must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to
the following figure). Once the Read command is registered, the data inputs will be ignored and writes will not
be executed.
The Read command that interrupts a write burst without auto precharge function should be issued one cycle
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
DOUT B2
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
READ B
NOP
DIN A0
DOUT B0
DOUT B1
CAS# latency=1
tCK1, DQ's
DOUT B3
don't care
DIN A0
DOUT B2
DOUT B0
DOUT B1
DOUT B3
DIN A0
don't care
don't care
DOUT B2
DOUT B0
DOUT B1
DOUT B3
Input data for the write is masked.
Write Interrupted by a Read
(Burst Length = 4, CAS# Latency = 1, 2, 3)
Input data must be removed rom the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
should be issued
m
cycles after the clock edge in which the last data-in element is registered, where
m
equals
t
WR
/t
CK
rounded up to the next whole number. In addition, the LDQM/UDQM signals must be used to mask input
data, starting with the clock edge following the last data-in element and ending with the clock edge on which the
BankPrecharge/PrechargeAll command is entered (refer to the following figure).
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function
CLK
T0
T 1
T2
T3
T4
T5
T6
WRITE
COMMAND
BANK (S)
ROW
NOP
NOP
Precharge
NOP
NOP
Activate
BANK
COL n
DIN
n
DIN
n + 1
DQM
ADDRESS
DQ
tWR
tRP
: don't care
Note:
The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
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