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| 型號： | T436432B-55SG |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| 中文描述： | 200萬× 32內(nèi)存為512k × 32 x 4Banks同步DRAM |
| 文件頁數(shù)： | 10/72頁 |
| 文件大小： | 731K |
| 代理商： | T436432B-55SG |
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TE
CH
tm
T436432B
TM Technology Inc. reserves the right
P. 10
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
DIN B2
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
WRITE B
NOP
DIN A0
DIN B0
DIN B1
DQ's
DIN B3
1 Clk Interval
Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)
cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input
data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs
(refer to the following figure). Once the Read command is registered, the data inputs will be ignored and writes
will not be executed.
The Read command that interrupts a write burst without auto precharge function should be issued one
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
READ B
NOP
DIN A0
don't care
DOUT B2
DOUT B0
DOUT B1
DOUT B3
DIN A0
don't care
don't care
DOUT B2
DOUT B0
DOUT B1
DOUT B3
Input data for the write is masked.
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
function should be issued
m
cycles after the clock edge in which the last data-in element is registered, where
m
equals t
WR
/t
CK
rounded up to the next whole number. In addition, the DQM signals must be used to mask input
data, starting with the clock edge following the last data-in element and ending with the clock edge on which
the BankPrecharge/PrechargeAll command is entered (refer to the following figure).
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge
CLK
T0
T 1
T2
T3
T4
T5
T6
WRITE
COMMAND
BANK (S)
ROW
NOP
NOP
Precharge
NOP
NOP
Activate
BANK
COL n
DIN
n
DIN
n + 1
DQM
ADDRESS
DQ
tWR
tRP
: don't care
Note:
The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
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| T436432B-5S | 制造商:TMT 制造商全稱:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
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