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| 型號： | T436432B-55SG |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| 中文描述： | 200萬× 32內(nèi)存為512k × 32 x 4Banks同步DRAM |
| 文件頁數(shù)： | 5/72頁 |
| 文件大小： | 731K |
| 代理商： | T436432B-55SG |
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TE
CH
tm
Operation Mode
T436432B
TM Technology Inc. reserves the right
P. 5
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
the truth table for the operation commands.
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows
Table 2. Truth Table (Note (1), (2) )
Command
State
CKE
n-1
CKE
n
DQM
(6)
BS
0,1
A
10
A
9-0
CS# RAS# CAS# WE#
BankActivate
Idle
(3)
H
X
X
V
Row address
L
L
H
H
BankPrecharge
Any
H
X
X
V
L
X
L
L
H
L
PrechargeAll
Any
H
X
X
X
H
X
L
L
H
L
Write
Active
(3)
H
X
X
V
L
L
H
L
L
Write and AutoPrecharge
Active
(3)
H
X
X
V
H
Column
address (A0
~ A7)
L
H
L
L
Read
Active
(3)
H
X
X
V
L
L
H
L
H
Read and Autoprecharge
Active
(3)
H
X
X
V
H
Column
address (A0
~ A7)
L
H
L
H
Mode Register Set
Idle
H
X
X
OP code
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
Burst Stop
Active
(4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
SelfRefresh Exit
Idle
L
H
X
X
X
X
H
X
X
X
(SelfRefresh)
L
H
H
H
Clock Suspend Mode Entry
Active
H
L
X
X
X
X
X
X
X
X
Power Down Mode Entry
Any
(5)
H
L
X
X
X
X
H
X
X
X
L
H
H
H
Clock Suspend Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
Power Down Mode Exit
Any
L
H
X
X
X
X
H
X
X
X
(PowerDown)
L
H
H
H
Data Write/Output Enable
Active
H
X
L
X
X
X
X
X
X
X
Data Mask/Output Disable
Note:
1. V = Valid, X = Don't care, L = Logic low, H = Logic high
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. DQM0-3
Active
H
X
H
X
X
X
X
X
X
X
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