參數(shù)資料
型號(hào): T436432B-55SG
廠商: TM Technology, Inc.
英文描述: 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM
中文描述: 200萬(wàn)× 32內(nèi)存為512k × 32 x 4Banks同步DRAM
文件頁(yè)數(shù): 8/72頁(yè)
文件大小: 731K
代理商: T436432B-55SG
TE
CH
tm
T436432B
TM Technology Inc. reserves the right
P. 8
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
CLK
DQM
COMMAND
DQ's
T0
T 1
T2
T3
T4
T5
T6
T7
T8
NOP
DOUT A0
DINB0
DINB1
DINB2
Must be Hi-Z before
the Write Command
: "H" or "L"
Read to Write Interval (Burst Length
4, CAS# Latency = 3)
CLK
DQM
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
ABANKA
DIN A0
DIN A1
DIN A2
DIN A3
1 Clk Interval
CAS# latency=2
tCK2, DQ's
: "H" or "L"
READ A
WRITE A
Read to Write Interval (Burst Length
4, CAS# Latency = 2)
CLK
DQM
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
NOP
READ A
NOP
WRITE B
NOP
NOP
NOP
DIN B0
DIN B1
DIN B2
DIN B3
CAS# latency=2
tCK2, DQ's
: "H" or "L"
NOP
NOP
Read to Write Interval (Burst Length
4, CAS# Latency = 2)
command to the same bank. The following figure shows the optimum time that BankPrecharge/ PrechargeAll
command is issued in different CAS# latency.
A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll
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