參數(shù)資料
型號: T436432B-7S
廠商: TM Technology, Inc.
英文描述: 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM
中文描述: 200萬× 32內存為512k × 32 x 4Banks同步DRAM
文件頁數(shù): 12/72頁
文件大?。?/td> 731K
代理商: T436432B-7S
TE
CH
tm
T436432B
TM Technology Inc. reserves the right
P. 12
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
RAS#
T0
T 1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
CKE
CS#
CAS#
WE#
ADDR.
DQM
DQ
tCK2
Clock min.
Address Key
t
RP
Hi-Z
PrechargeAll
Mode Register
Set Command
Mode Register Set Cycle (CAS# Latency = 2, 3)
Any
Command
The mode register is divided into various fields depending on functionality.
Address BS0,1 A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function RFU*
RFU*
WBL
Test Mode
CAS Latency
BT
Burst Length
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2,
4, 8, or full page.
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Burst Length
1
2
4
8
Reserved
Reserved
Reserved
Full Page
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