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參數(shù)資料
| 型號： | T436432B-7S |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| 中文描述： | 200萬× 32內(nèi)存為512k × 32 x 4Banks同步DRAM |
| 文件頁數(shù)： | 9/72頁 |
| 文件大?。?/td> | 731K |
| 代理商： | T436432B-7S |
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TE
CH
tm
T436432B
TM Technology Inc. reserves the right
P. 9
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
CLK
COMMAND
CAS# latency=2
tCK2, DQ's
T0
T 1
T2
T3
T4
T5
T6
T7
T8
READ A
NOP
NOP
NOP
NOP
Activate
NOP
NOP
Precharge
CAS# latency=3
tCK3, DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
ADDRESS
t
RP
Bank,
Col A
Bank(s)
Bank,
Row
Read to Precharge (CAS# Latency = 2, 3)
5
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the read
operation. Once this command is given, any subsequent command cannot occur within a time delay of
{
t
RP
(min.)
+ burst length
}
. At full-page burst, only the read operation is performed in this command and the auto precharge
function is ignored.
6
Write command
(RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least t
RCD
(min.) before the Write command is issued. During write
bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data
elements will be registered on each successive positive clock edge (refer to the following figure). The DQs
remain with high-impedance at the end of the burst unless another command is initiated. The burst length and
burst sequence are determined by the mode register, which is already programmed. A full-page burst will
continue until terminated (at the end of the page it will wrap to column 0 and continue).
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
DIN A3
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DQ0 - DQ3
The first data element and the write
are registered on the same clock edge.
Extra data s masked.
don't care
Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from
Write command can occur on any clock cycle following the previous Write command (refer to the following
figure).
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write,
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| T436432B-7SG | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-8S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-8SG | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-10S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
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| T436432B-7SG | 制造商:TMT 制造商全稱:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
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