- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361344 > T436432B-7S (TM Technology, Inc.) 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號： | T436432B-7S |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| 中文描述： | 200萬× 32內(nèi)存為512k × 32 x 4Banks同步DRAM |
| 文件頁數(shù)： | 15/72頁 |
| 文件大小： | 731K |
| 代理商： | T436432B-7S |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
TE
CH
tm
11 Device Deselect command (CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and
Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No
Operation command.
T436432B
TM Technology Inc. reserves the right
P. 15
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
12 AutoRefresh command
(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", BS0,1 = “Don‘t care, A0-A10 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-
before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be issued
each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the
address bits a "don't care" during an AutoRefresh command. The internal refresh counter increments
automatically on every auto refresh cycle to all of the rows. The refresh operation must be performed 4096
times within 64ms. The time required to complete the auto refresh operation is specified by t
RC
(min.). To
provide the AutoRefresh command, all banks need to be in the idle state and the device must not be in power
down mode (CKE is high in the previous cycle). This command must be followed by NOPs until the auto
refresh operation is completed. The precharge time requirement, t
RP
(min), must be met before successive auto
refresh operations are performed.
13 SelfRefresh Entry command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A10 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for data
retention and low power operation. Once the SelfRefresh command is registered, all the inputs to the SDRAM
become "don't care" with the exception of CKE, which must remain LOW. The refresh addressing and timing is
internally generated to reduce power consumption. The SDRAM may remain in SelfRefresh mode for an
indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on
CKE (SelfRefresh Exit command).
14 SelfRefresh Exit command
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or
Device Deselect commands must be issued for t
RC
(min.) because time is required for the completion of any
bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation,
a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the
SelfRefresh mode.
15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while
CLK is suspended. On the other hand, when all banks are in the idle state, this command performs entry into
the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown
mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period
(64ms) since the command does not perform any refresh operations.
16 Clock Suspend Mode Exit / PowerDown Mode Exit command
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the
subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the PowerDown
mode, the device exits this mode and all disabled buffers are turned on to the active state. t
PDE
(min.) is required
when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock
cycle from the end of this command.
17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")
During a write cycle, the DQM signal functions as a Data Mask and can control every word of the input
data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device
selection, byte selection and bus control in a memory system.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T436432B-7SG | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-8S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-8SG | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-10S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T436432B-7SG | 制造商:TMT 制造商全稱:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-8S | 制造商:TMT 制造商全稱:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-8SG | 制造商:TMT 制造商全稱:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T4365 250 | 制造商:CK tools 功能描述:WRENCH 10 制造商:CK tools 功能描述:WRENCH, 10 |
| T4365-12 | 制造商:CK tools 功能描述:WRENCH 12" 制造商:CK tools 功能描述:WRENCH, 12" 制造商:CK TOOLS 功能描述:WRENCH, 12"; AF Size - Metric:38mm; Length:300mm; Jaw Opening Max:38mm; SVHC:No SVHC (19-Dec-2012); Length (Imperial):12" ;RoHS Compliant: NA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。