- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361344 > T436432B-8SG (TM Technology, Inc.) 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | T436432B-8SG |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| 中文描述： | 200萬× 32內(nèi)存為512k × 32 x 4Banks同步DRAM |
| 文件頁數(shù)： | 6/72頁 |
| 文件大?。?/td> | 731K |
| 代理商： | T436432B-8SG |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
TE
CH
tm
Commands
T436432B
TM Technology Inc. reserves the right
P. 6
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
1
BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BS = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal. By
latching the row address on A0 to A10 at the time of this command, the selected row access is initiated. The
read or write operation in the same bank can occur after a time delay of t
RCD
(min.) from the time of bank
activation. A subsequent BankActivate command to a different row in the same bank can only be issued after
the previous active row has been precharged (refer to the following figure). The minimum time interval
between successive BankActivate commands to the same bank is defined by t
RC
(min.). The SDRAM has four
internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts
the back-to-back activation of the four banks. t
RRD
(min.) specifies the minimum time required between
activating different banks. After this command is used, the Write command and the Block Write command
perform the no mask write operation.
CLK
ADDRESS
T0
T 1
T2
T3
Tn+3
Tn+4
Tn+5
Tn+6
..............
COMMAND
..............
..............
NOP
NOP
NOP
NOP
RAS# - CAS# delay (
t
RCD
)
RAS# - RAS# delay time (
t
RRD
)
RAS# Cycle time (
t
RC
)
Bank A
Row Addr.
Bank A
Col Addr.
Bank B
Row Addr.
Bank A
Row Addr.
Bank A
Activate
R/W A with
AutoPrecharge
Bank B
Activate
Bank A
Activate
AutoPrecharge
Begin
: "H" or "L"
BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3)
2
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BS = Bank, A10 = "L", A0-A9 = Don't care)
The BankPrecharge command precharges the bank disignated by BS0,1 signal. The precharged bank is
switched from the active state to the idle state. This command can be asserted anytime after t
RAS
(min.) is
satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is
specified by t
RAS
(max.). Therefore, the precharge function must be performed in any active bank within
t
RAS
(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be activated
again.
3
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BS = Don’t care, A10 = "H", A0-A9 = Don't care)
The PrechargeAll command precharges all the four banks simultaneously and can be issued even if all
banks are not in the active state. All banks are then switched to the idle state.
4
Read command
(RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least t
RCD
(min.) before the Read command is issued. During read
bursts, the valid data-out element from the starting column address will be available following the CAS#
latency after the issue of the Read command. Each subsequent data-out element will be valid by the next
positive clock edge (refer to the following figure). The DQs go into high-impedance at the end of the burst
unless other command is initiated. The burst length, burst sequence, and CAS# latency are determined by the
mode register which is already programmed. A full-page burst will continue until terminated (at the end of the
page it will wrap to column 0 and continue).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T436432B | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-10S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-10SG | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-55S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-55SG | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T4365 250 | 制造商:CK tools 功能描述:WRENCH 10 制造商:CK tools 功能描述:WRENCH, 10 |
| T4365-12 | 制造商:CK tools 功能描述:WRENCH 12" 制造商:CK tools 功能描述:WRENCH, 12" 制造商:CK TOOLS 功能描述:WRENCH, 12"; AF Size - Metric:38mm; Length:300mm; Jaw Opening Max:38mm; SVHC:No SVHC (19-Dec-2012); Length (Imperial):12" ;RoHS Compliant: NA |
| T4365-6 | 制造商:CK tools 功能描述:WRENCH 6" 制造商:CK tools 功能描述:WRENCH, 6" 制造商:CK TOOLS 功能描述:WRENCH, 6"; AF Size - Metric:24mm; Length:150mm; Jaw Opening Max:24mm; SVHC:No SVHC (19-Dec-2012); Length (Imperial):6" ;RoHS Compliant: NA |
| T4365-8 | 制造商:CK tools 功能描述:WRENCH 8" 制造商:CK tools 功能描述:WRENCH, 8" 制造商:CK TOOLS 功能描述:WRENCH, 8"; AF Size - Metric:29mm; Length:200mm; Jaw Opening Max:29mm; SVHC:No SVHC (19-Dec-2012); Length (Imperial):8" ;RoHS Compliant: NA |
| T43D | 制造商:WELWYN 制造商全稱:Welwyn Components Limited 功能描述:High Voltage Precision Thick Film Resistors |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。