參數(shù)資料
型號： T7256A
英文描述： Compliance with the New ETSI PSD Requirement
中文描述： 符合新的ETSI PSD的要求
文件頁數(shù)： 31/116頁
文件大?。?/td> 1056K
代理商： T7256A
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
27
Microprocessor Interface Description
(continued)
Registers
(continued)
Table 9. TDM Bus Timing Control (Address 05h)
Bits 0—4 are enabled only if TDMEN = 0 (register GR2, bit 5) and one or more of bits DFR1[2:7] are set to 0.
Reg
TDR0
R/W
R/W
Bit 7
—
—
Bit 6
—
—
Bit 5
—
—
Bit 4
—
—
Bit 3
FSP
1
Bit 2
FSC2
1
Bit 1
FSC1
1
Bit 0
FSC0
1
Default State on RESET
Register
TDR0
Bit
2—0
Symbol
FSC[2:0]
Name/Description
Frame Strobe (FS) Control.
Selects location of strobe envelope within
TDM bus time slots.
000—S/T-interface 2B+D channel strobe (18-bit envelope).
001—U-interface 2B+D channel strobe (18-bit envelope).
010—S/T-interface B2 channel strobe (8-bit envelope).
011—U-interface B2 channel strobe (8-bit envelope).
100—S/T-interface D channel strobe (2-bit envelope).
101—U-interface D channel strobe (2-bit envelope).
110—S/T-interface B1 channel strobe (8-bit envelope).
111—U-interface B1 channel strobe (8-bit envelope) (default).
Frame Strobe (FS) Polarity.
0—Active-low envelope.
1—Active-high envelope (default).
TDR0
3
FSP
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