參數(shù)資料
型號(hào)： T7256A
英文描述： Compliance with the New ETSI PSD Requirement
中文描述： 符合新的ETSI PSD的要求
文件頁數(shù)： 36/116頁
文件大小： 1056K
代理商： T7256A
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
32
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Registers
(continued)
Table 14. eoc State Machine Control—Information (Address 0Ah)
This register has no effect on device operation if AUTOEOC = 1 (register GR0, bit 4).
Table 15. eoc State Machine Status—Address (Address 0Bh)
This register contains the currently received eoc address and data/message indicator bits independent of the state
of AUTOEOC (register GR0, bit 4).
Table 16. eoc State Machine Status—Information (Address 0Ch)
This register contains the currently received eoc information bits independent of the state of AUTOEOC (register
GR0, bit 4).
Reg
ECR1
R/W
R/W
Bit 7
I1T
1
Bit 6
I2T
1
Bit 5
I3T
1
Bit 4
I4T
1
Bit 3
I5T
1
Bit 2
I6T
1
Bit 1
I7T
1
Bit 0
I8T
1
Default State on RESET
Register
ECR1
Bit
0—7
Symbol
I[8:1]T
Name/Description
Transmit eoc Information.
These bits are transmitted as the eoc chan-
nel message when in manual eoc mode.
See eoc State Machine Description section for a list of possible eoc
messages.
Reg
ECR2
R/W
R
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
DMR
Bit 2
A1R
Bit 1
A2R
Bit 0
A3R
Register
ECR2
Bit
0—2
Symbol
A[3:1]R
Name/Description
Receive eoc Address.
These bits store the received eoc address.
000 = NT address.
001—110 = Intermediate element addresses.
111 = Broadcast address.
Receive eoc Data or Message Indicator.
0—Data.
1—Message.
ECR2
3
DMR
Reg
ECR3
R/W
R
Bit 7
I1R
Bit 6
I2R
Bit 5
I3R
Bit 4
I4R
Bit 3
I5R
Bit 2
I6R
Bit 1
I7R
Bit 0
I8R
Register
ECR3
Bit
0—7
Symbol
I[8:1]R
Name/Description
Receive eoc Information.
Receive eoc channel message or data.
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