參數(shù)資料
型號： T8531A
元件分類： Codec
英文描述： T8531A/8532 Multichannel Programmable Codec Chip Set
中文描述： T8531A/8532多通道可編程解碼器芯片組
文件頁數(shù)： 11/50頁
文件大?。?/td> 888K
代理商： T8531A
Agere Systems Inc.
11
Preliminary Data Sheet
September 2001
Codec Chip Set
T8531A/T8532 Multichannel Programmable
Pin Information
(continued)
Table 2. T8531A Pin Descriptions
(continued)
* The DSP is
not
configured for boundary scan operation.
Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; I
u
indicates that a pull-
up device is included on this lead, I
d
indicates that a pull-down device is included on this lead.
Number
23
Name
SDX
Type
TO
Name/Function
Transmit PCM Output.
This pin remains in the high-impedance state
except during the transmit time slots as defined in the TSA registers.
Data is shifted out on the rising edge of SCK.
Frame Sync.
Active-high pulse or square wave with an 8 kHz pulse
repetition rate. The rising edge defines the start of the transmit and
receive frames.
T8532 Control Data Output
. Control register information for the T8532
chips. Data is valid only when either CCS0 or CCS1 is low.
T8532 Control Data Input
. Control register information from the T8532
chips. Data is valid only when either CCS0 or CCS1 is low. An internal
pull-up device is provided.
Control Interface Chip Select (Active-Low).
These active-low outputs
select one of the associated T8532 chips.
JTAG Test Port
*
-Common Test Clock.
Rate
≤
20 MHz.
JTAG Test Port
*
-Serial Data Input.
A pull-up device is provided.
JTAG Test Port
*
-Serial Data Output.
JTAG Test Port
*
-Mode Select.
A pull-up device is provided.
JTAG Test.
Used for factory testing. Do not make any connection to this
pin. A pull-up device is provided.
3-State Control Pin (Active-Low).
When pulled low, the device output
pins go into a high-impedance state. A pull-up device is provided.
Test Mode Input (Active-Low).
This input allows bypass of clock synthe-
sizer and uses TSTCLK to drive the chip. A pull-up device is provided.
16 MHz Clock Output.
16.384 MHz clock output (50% duty cycle). This
clock is present at all times and can be used to drive a host processor.
Test Clock.
No Connect.
This pin may be used as a tie point.
Test Sync (Active-Low).
Used for factory testing. Do not make any con-
nection to this pin. A pull-up device is provided.
Reset (Active-Low).
A logic low initiates reset. A pull-up device is pro-
vided.
5 V Digital Power Supply.
Power supply decoupling capacitors (0.1
μ
F)
should be connected from each V
DD
pin to ground. Capacitors should be
located as close as possible to the device pins.
Digital Ground.
21
SFS
TI
54
CDO
CO
51
CDI
TI
u
53, 52
CCS[1:0]
CO
7
4
5
6
48
TCK
TDI
TDO
TMS
JTESTB
TI
TI
u
TO
TI
u
TI
u
59
HIGHZB
TI
u
60
TEST
CI
u
61
CK16
CO
8
TSTCLK
NC
T_SYNC
CI
—
CI
u
1, 12, 14, 64
55
58
RSTB
TI
u
3, 10, 16, 19,
25, 31, 34, 46,
50, 56, 62
2, 9, 15, 18, 26,
32, 33, 41, 47,
49, 57, 63
V
DD
—
V
SS
—
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T8532 制造商:AGERE 制造商全稱:AGERE 功能描述:T8531A/8532 Multichannel Programmable Codec Chip Set
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T85331J 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks
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