參數(shù)資料
型號(hào)： T8531A
元件分類： Codec
英文描述： T8531A/8532 Multichannel Programmable Codec Chip Set
中文描述： T8531A/8532多通道可編程解碼器芯片組
文件頁(yè)數(shù)： 50/50頁(yè)
文件大小： 888K
代理商： T8531A
Preliminary Data Sheet
September 2001
Codec Chip Set
T8531A/T8532 Multichannel Programmable
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright 2001 Agere Systems Inc.
All Rights Reserved
September 2001
DS01-320ALC (Replaces DS01-030ALC)
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
http://www.agere.com
E-MAIL:
docmaster@agere.com
N. AMERICA:
Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447
, FAX 610-712-4106 (In CANADA:
1-800-553-2448
, FAX 610-712-4106)
ASIA:
Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000
, FAX (852) 3129-2020
CHINA:
(86) 21-5047-1212
(Shanghai),
(86) 10-6522-5566
(Beijing),
(86) 755-695-7224
(Shenzhen)
JAPAN:
(81) 3-5421-1600
(Tokyo), KOREA:
(82) 2-767-1850
(Seoul), SINGAPORE:
(65) 778-8833
, TAIWAN:
(886) 2-2725-5858
(Taipei)
EUROPE:
Tel. (44) 7000 624624
, FAX (44) 1344 488 045
Ordering Information
Appendix A. Transmit Path Group Delay vs. Bit Offset
Receive path group delay is a fixed value and is specified in the data sheet.
Note:
Bit offset values for partial time segments would incrementally add to the base data delay value by 488 ns
per bit offset for an SCK of 2.048 MHz and in increments of 244 ns per bit offset for an SCK of 4.096 MHz.
Table 42. Transmit Path Group Delay vs. Bit Offset
Telcordia Technologiesis a trademark of Telcordia Technologies, Inc.
Device Code
T-8531A - - - TL-DB
T-8531A - - - TL-DT
T-8532 - - - JL-DB
T-8532 - - - JL-DT
Package
Temperature
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
Comcode
108888272
108888678
108697301
700005740
64-Pin TQFP, Dry pack tray
64-Pin TQFP, Dry-bagged, Tape & Reel
64-Pin MQFP, Dry pack tray
64-Pin MQFP, Dry-bagged, Tape & Reel
Bit Offset in Whole Time
Segments
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit Offset
SCK = 2.048 MHz
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
Bit Offset
SCK = 4.096 MHz
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
T
X
Data Delay (μs)
f = 1600 Hz
273.4
281.2
289.0
296.8
304.6
312.4
320.2
328.0
335.8
343.6
351.4
359.2
367.0
250.0
257.8
265.6
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T8532 制造商:AGERE 制造商全稱:AGERE 功能描述:T8531A/8532 Multichannel Programmable Codec Chip Set
T8533 制造商:AGERE 制造商全稱:AGERE 功能描述:T8533/34 Quad Programmable Line Card Signal Processor
T85331G 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks
T85331J 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks
T8534 制造商:AGERE 制造商全稱:AGERE 功能描述:T8533/34 Quad Programmable Line Card Signal Processor
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