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參數(shù)資料
| 型號： | T8531A |
| 元件分類： | Codec |
| 英文描述： | T8531A/8532 Multichannel Programmable Codec Chip Set |
| 中文描述： | T8531A/8532多通道可編程解碼器芯片組 |
| 文件頁數(shù)： | 33/50頁 |
| 文件大?。?/td> | 888K |
| 代理商： | T8531A |
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Agere Systems Inc.
33
Preliminary Data Sheet
September 2001
Codec Chip Set
T8531A/T8532 Multichannel Programmable
Software Interface
Table 18 lists the RAM data space for the DSP engine. Space for up to 16 channels is allocated. The total T8531A
RAM size is 4 Kwords, arranged as 4 x 1 Kbanks. Address bit 15 is used as a read/write flag (1 = read). The micro-
processor interface can read any address in the DSP engine RAM space.
Table 18. DSP Engine RAM Memory Map
1. This address can address ROM code.
2.
For time slots 1—15, the address shown is the first address. Refer to time slot 0 for range information.
3. For channels 1—15, the address shown is the first address. Refer to channel 0 for range information.
Address Range
RAM Bank 0
0x0000
0x0001
1
0x0002
1
0x0003—0x003F
0x0040
2
0x0080
0x00C0
0x0100
0x0140
0x0180
0x01C0
0x0200
0x0240
0x0280
0x02C0
0x0300
0x0340
0x0380
0x03C0
RAM Bank 1
0x0400—0x040F
0x0410—0x0413
0x0414—0x0434
Memory Contents
Time-Slot Information Tables
(See page 18.)
Time-slot control word (time slot 0)
Receive ac routine address (time slot 0)
Transmit ac routine address (time slot 0)
Data storage (time slot 0)
Time slot 1 information table
Time slot 2 information table
Time slot 3 information table
Time slot 4 information table
Time slot 5 information table
Time slot 6 information table
Time slot 7 information table
Time slot 8 information table
Time slot 9 information table
Time slot 10 information table
Time slot 11 information table
Time slot 12 information table
Time slot 13 information table
Time slot 14 information table
Time slot 15 information table
ac Coefficient Reference Tables
Channel coefficient address table
Default coefficient address table
Reserved
ac Per-Channel Coefficients
(See page 17.)
Receive path relative gain (channel 0)
Data storage (channel 0)
Receive path absolute gain (channel 0)
Transmit path absolute gain (channel 0)
Balance filter coefficients (channel 0)
Data storage (channel 0)
Transmit path relative gain (channel 0)
Channel 1 ac filter coefficients
Channel 2 ac filter coefficients
Channel 3 ac filter coefficients
Channel 4 ac filter coefficients
Channel 5 ac filter coefficients
Channel 6 ac filter coefficients
Channel 7 ac filter coefficients
Write by Microprocessor Interface
Y
Y
Y
Selected locations
As shown for time slot 0
As shown for time slot 0
As shown for time slot 0
As shown for time slot 0
As shown for time slot 0
As shown for time slot 0
As shown for time slot 0
As shown for time slot 0
As shown for time slot 0
As shown for time slot 0
As shown for time slot 0
As shown for time slot 0
As shown for time slot 0
As shown for time slot 0
As shown for time slot 0
N
N
N
0x0435
0x0436
0x0437
0x0438
Y
N
Y
Y
Y
N
Y
0x0439—0x0442
0x0443
0x0444
0x0445
3
0x0455
0x0465
0x0475
0x0485
0x0495
0x04A5
As shown for channel 0
As shown for channel 0
As shown for channel 0
As shown for channel 0
As shown for channel 0
As shown for channel 0
As shown for channel 0
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PDF描述 |
|---|---|
| T8531 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8532 | T8502 and T8503 Dual PCM Codecs with Filters |
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| T8534 | T8533/34 Quad Programmable Line Card Signal Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T8532 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8531A/8532 Multichannel Programmable Codec Chip Set |
| T8533 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8533/34 Quad Programmable Line Card Signal Processor |
| T85331G | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
| T85331J | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
| T8534 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8533/34 Quad Programmable Line Card Signal Processor |
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