參數(shù)資料
型號(hào): T89C51CC02UA-SITIM
廠商: Atmel
文件頁數(shù): 71/159頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 16K 28PLCC
標(biāo)準(zhǔn)包裝: 37
系列: AT89C CAN
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-PLCC
包裝: 管件
配用: AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱: T89C51CC02UASITIM
19
AT/T89C51CC02
4126L–CAN–01/08
Register
Table 12. CKCON Register
CKCON (S:8Fh)
Clock Control Register
Note:
1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit
has no effect.
Reset Value = 0000 0000b
765
43210
CANX2
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Number
Bit
Mnemonic
Description
7CANX2
CAN Clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
6WDX2
Watchdog Clock
(1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5PCAX2
Programmable Counter Array Clock
(1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
4SIX2
Enhanced UART clock (MODE 0 and 2)
(1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
3T2X2
Timer 2 Clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2T1X2
Timer 1 Clock
(1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
1T0X2
Timer 0 Clock
(1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
0X2
CPU Clock
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all
the peripherals.
Set to select 6 clock periods per machine cycle (X2 Mode) and to enable the
individual peripherals ’X2’ bits.
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