參數(shù)資料
型號(hào): T89C51CC02UA-SITIM
廠商: Atmel
文件頁數(shù): 79/159頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 16K 28PLCC
標(biāo)準(zhǔn)包裝: 37
系列: AT89C CAN
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 2K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-PLCC
包裝: 管件
配用: AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱: T89C51CC02UASITIM
26
AT/T89C51CC02
4126L–CAN–01/08
Data Memory
The T89C51CC02 provides data memory access in two different spaces:
The internal space mapped in three separate segments:
The lower 128 Bytes RAM segment.
The upper 128 Bytes RAM segment.
The expanded 256 Bytes RAM segment (XRAM).
A fourth internal segment is available but dedicated to Special Function Registers,
SFRs, (addresses 80h to FFh) accessible by direct addressing mode.
Figure 9 shows the internal data memory spaces organization.
Figure 9. Internal memory - RAM
Internal Space
Lower 128 Bytes RAM
The lower 128 Bytes of RAM (See Figure 10) are accessible from address 00h to 7Fh
using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4
banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (See Table 18)
select which bank is in use according to Table 17. This allows more efficient use of code
space, since register instructions are shorter than instructions that use direct address-
ing, and can be used for context switching in interrupt service routines.
Table 17. Register Bank Selection
The next 16 Bytes above the register banks form a block of bit-addressable memory
space. The C51 instruction set includes a wide selection of singlebit instructions, and
the 128 bits in this area can be directly addressed by these instructions. The bit
addresses in this area are 00h to 7Fh.
256 Bytes
Upper
128 Bytes
Internal RAM
Lower
128 Bytes
Internal RAM
Special
Function
Registers
80h
00h
FFh
00h
FFh
Direct Addressing
Addressing
7Fh
Internal XRAM
Direct or Indirect
Indirect Addressing
RS1
RS0
Description
0
Register bank 0 from 00h to 07h
0
1
Register bank 0 from 08h to 0Fh
1
0
Register bank 0 from 10h to 17h
1
Register bank 0 from 18h to 1Fh
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