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參數(shù)資料
| 型號： | T90FJR |
| 廠商： | ATMEL CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Dual Common Interface Hardware Controller- CIMax |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 10/41頁 |
| 文件大?。?/td> | 617K |
| 代理商： | T90FJR |
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10
T90FJR
Rev. A
–
7-Sep-01
Figure 3.
Read access
Notes:
1. The WAIT/ACK output is either WAIT or ACK formatted according to the WAIT/ACK
pin settings (active level, driving structure).
2. Depending on the read access type, CE can be either CE1A# or CE1B# for access to
memory or IO to module A or B, CE2A# or CE2B# for access in EC (Extended Chan-
nel) mode, or even EXTCS for access to external device in regenerate mode.
3. REG# signal is not asserted during a common memory or external access.
4. OE# signal is asserted during a memory access (attribute or common). It is replaced
by IORD# during an IO read cycle, an EC (Extended Channel) read cycle (using
CE2A# or CE2B#) or an external access in regenerate mode.
5. t4 can be lengthened by the insertion of wait cycles. When the destination module
asserts WAIT# signal, the t4 cycles counter stops until WAIT# becomes inactive
anew.
Memory read timings are given for various cycle duration. In attribute memory mode,
only 600ns and 300ns cycles are available. In common memory mode, 300ns doesn
’
t
exist. IO and external device in regenerate mode share the same timing specifications
as they all use IORD# and IOWR# signals. Timings are given in CIMaX
clock cycles.
They are calculated to comply with PCMCIA specifications when 27MHz clock is used.
t7
RD
’
WAIT
(1)
ACK
(1)
CE
(2)
REG#
(3)
OE#
(4)
ADLE
DATDIR
DATOE#
t2
t3
t4
(5)
t6
t1
t5
t8
t10
t9
t0
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