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參數(shù)資料
| 型號： | T90FJR |
| 廠商： | ATMEL CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Dual Common Interface Hardware Controller- CIMax |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 29/41頁 |
| 文件大小： | 617K |
| 代理商： | T90FJR |
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29
T90FJR
Rev. A
–
7-Sep-01
Interrupt config register: (@1Ch)
EXTLVL
EXTINT input pin active level
changing this bit is only allowed when LOCK = 0
0
EXTINT pin is active-low
1
EXTINT pin is active-high
ITLVL
INT output pin active level
changing this bit is only allowed when LOCK = 0
0
INT pin is active-low
1
INT pin is active-high
ITDRV
INT output pin structure
changing this bit is only allowed when LOCK = 0
0
INT buffer is open drain
1
INT buffer is push-pull
UCSG1 and UCSG2
Registers
The UCSG1 and UCSG2 Registers generate PC Card control signals (REG#, OE#,
WE#, IORD#, IOWR#, CE1/2A#, CE1/2B#) from microprocessor control signals
(RD/DIR, WR/STR, WAIT/ACK, CS, A[25..15]).
UCSG1 Register : (@1Dh)
RDIR
RD/DIR and WR/STR inputs function
changing this bit is only allowed when LOCK = 0
0
RD/WR mode
1
DIR/STR mode
RDIRLVL
RD/DIR input active level (for read strobe or read direction)
changing this bit is only allowed when LOCK = 0
0
RD is active-low or RD/DIR input is low during read transfer and high during write
1
RD is active-high or RD/DIR input is high during read transfer and low during write
WSTRLVL
WR/STR input active level
changing this bit is only allowed when LOCK = 0
0
WR/STR is active-low
1
WR/STR is active-high
X
X
X
X
X
ITDRV
ITLVL
EXTLVL
X
X
X
X
CSLVL
WSTRLVL
RDIRLVL
RDIR
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