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參數(shù)資料
| 型號： | T90FJR |
| 廠商： | ATMEL CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Dual Common Interface Hardware Controller- CIMax |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 14/41頁 |
| 文件大?。?/td> | 617K |
| 代理商： | T90FJR |
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14
T90FJR
Rev. A
–
7-Sep-01
Note:
1. these timings are given for a load of 50 pF on WAIT/ACK pin.
2. 1.5 cycle corresponds to the start cycle detection time. t1 depends actually on the
previous cycle completion which depends on t8 and t10 read timings. So t1 ranges
from 3.5 to 6.5 cycles.
t0: delay between start of a write cycle and activation of WAIT
t1: delay between start of a write cycle and assertion of CE and REG# (if necessary for
the current cycle)
t2: delay to assertion of the write signal (WE# or IOWR#) after the start of the write cycle
t3: delay to assertion of the write signal (WE# or IOWR#) after the assertion of CE
t4: write cycle duration. This delay can be lengthened by the assertion of the module
WAIT# pin
t5: delay between deassertion of the write signal and deassertion of CE, REG# and
WAIT and assertion of ACK indicating to the processor the end of its write cycle
t6: delay between end of the write cycle and deassertion of ACK
t7: delay between enabling of the data bus and write signal assertion. This delay is nec-
essary when a write cycle is immediately following a read cycle (see t10 in read cycle)
Note:
The corresponding timings are given below for a 27 MHz clock:
Memory write
IO,
EC,
Ext
600ns
250ns
200ns
150ns
100n
s
t0 max
(1)
26 ns
t1 max
1.5 cycle + 26 ns
(2)
t2 min
2
1
1
1
1
2
t3
2
1
1
1
1
2
t4
9
5
4
3
2
5
t5
2
1
1
1
1
1
t6 max
(1)
26 ns
t7 min
1
1
1
1
1
2
Memory write
IO,
EC,
Ext
600ns
250ns
200ns
150ns
100n
s
t0 max
24 ns
t1 max
80 ns
(from start cycle detection
–
see note in table above)
t2 min
75 ns
37 ns
37 ns
37 ns
37
ns
75
ns
t3
75 ns
37 ns
37 ns
37 ns
37
ns
75
ns
t4
334 ns
185 ns
150
ns
111 ns
75
ns
185
ns
t5
75 ns
37 ns
37 ns
37 ns
37
ns
37
ns
t6 max
26 ns
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