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參數(shù)資料
| 型號： | TA2159F |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic |
| 中文描述： | 東芝雙極線性集成電路硅單片 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 378K |
| 代理商： | TA2159F |
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TA2159F
2002-10-03
9
PIN
No.
Symbol
Pin Name
Function and Operation
Remarks
18
SLEEP
Sleep input
If SLEEP Low while V
DD
is being
applied, the device enters Ultra-Low
Current Dissipation mode where memory
only is backed up by stopping crystal
oscillation, PLL, and the CPU.
At that time, V
DD
can be dropped to 0.75
V.
When V
DD
is less than 0.75 V, this
function will be reset. The minimum
frequency 87.5 MHz or 76 MHz will be set
at transmission mode on power on.
To restore from back-up state, set the pin
from Low to High. Turn the radio on at the
same time.
19
IF IN
IF signal input
IF signal input pin for the IF counter to
count the IF signals of the FM band and to
detect the automatic stop positon.
The input frequency is between 0.3 to 12
MHz. A built-in input amp.and C coupling
allow operation at low-level input.
Note: The internal IF amp is operated
whether the IF counter is ON or
OFF, and the noise level will be
increased. Toshiba recommend
connect the pin to GND using the
pin 7 (IF-NOISE) signal at normal
operation.
13, 22
V
DD
20, 35
GND
Power-supply
pins
Power supply pins.
Normally, V
DD
3.0 V is applied.
21
FM IN
local
oscillation
signal input
Direct division method.
Input range: 5 to 8 MHz
Note: In PLL OFF mode, input is at high
impedance.
23
DO
Phase
comparator
output
PLL phase comparator output pin.
Tri-state output.
When programmable counter divided
frequency output is higher than the
reference frequency, High level is output;
when lower, Low level is output; when
they match, high impedance. When the
radio is off, output Low is fixed.
19
V
DD
R
fIN1
18
V
DD
23
V
DD
13, 22
20, 35
21
V
DD
R
fIN1
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