參數(shù)資料
型號： TAS5508PAGRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁數(shù)： 52/105頁
文件大?。?/td> 1286K
代理商： TAS5508PAGRG4
3.3.7
Modulation Index Limit
3.3.8
Interchannel Delay
3.4
Master Clock and Serial Data Rate Controls
TAS5508
8-Channel Digital Audio PWM Processor
SLES091D – FEBRUARY 2004 – REVISED JULY 2009
www.ti.com
Table 3-8. Volume Ramp Rates in ms
SAMPLE RATE (kHz)
NUMBER OF STEPS
44.1, 88.2, 176.4
32, 48, 96, 192
512
46.44 ms
42.67 ms
1024
92.88 ms
85.33 ms
2048
185.76 ms
170.67 ms
PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation
is 50%. When the audio signal increases toward full scale, the PWM modulation increases toward 100%.
For negative signals, the PWM modulations fall below 50% toward 0%.
However, there is a limit to the maximum modulation possible. During the offtime period, the power stage
connected to the TAS5508 output needs to get ready for the next ontime period. The maximum possible
modulation is then set by the power stage requirements. All Texas Instruments power stages need
maximum modulation to be 97.7%. This is also the default setting of the TAS5508. Default settings can be
changed in the modulation index register (0x16).
Note that no change should be made to this register when using Texas Instruments power stages.
An 8-bit value can be programmed into each of the eight PWM interchannel delay registers to add a delay
per channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock,
DCLK. The default values are shown in Table 3-9.
Table 3-9. Interchannel Delay Default Values
I2C SUBADDRESS
CHANNEL
INTERCHANNEL DELAY DEFAULT (DCLK PERIODS)
0x1B
1
–24
0x1C
2
0
0x1D
3
–16
0x1E
4
16
0x1F
5
–24
0x20
6
8
0x21
7
–8
0x22
8
24
This delay is generated in the PWM and can be changed at any time through the serial-control interface
I2C registers 0x1B–0x22. The absolute offset for channel 1 is set in I2C subaddress 0x23.
NOTE
If used correctly, setting the PWM channel delay can optimize the performance of a
PurePath Digital amplifier system. The setting is based on both the type of back-end
power device that is used and the layout. These values are set during initialization using
the I
2C serial interface. Unless otherwise noted, use the default values given in Table 3-9.
The TAS5508 functions only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK
(left/right clock) signals that control the flow of data on the four serial data interfaces. The 13.5-MHz
external crystal allows the TAS5508 to detect MCLK and the data rate automatically.
The MCLK frequency can be 64
＝ Fs, 128 ＝ Fs, 196 ＝ Fs, 256 ＝ Fs, 384 ＝ Fs, 512 ＝ Fs, or 768 ＝
Fs.
TAS5508 Controls and Status
50
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