參數(shù)資料
型號(hào)： TAS5508PAGRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 70/105頁(yè)
文件大?。?/td> 1286K
代理商： TAS5508PAGRG4
5.5
Incremental Multiple-Byte Write
5.6
Single-Byte Read
A6
A5
A0 R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A0
ACK
Start
Condition
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
DataByte
D7
D6
D1
D0 ACK
I CDevice Addressand
Read/WriteBit
2
Not
Acknowledge
R/W
A1
RepeatStart
Condition
T0036-03
TAS5508
8-Channel Digital Audio PWM Processor
www.ti.com
SLES091D – FEBRUARY 2004 – REVISED JULY 2009
The I2C supports a special mode which permits I2C write operations to be broken up into multiple data
write operations that are multiples of four data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc.,
write operations that are composed of a device address, read/write bit, subaddress, and any multiple of
four bytes of data. This permits the system to write large register values incrementally without blocking
other I2C transactions.
This feature is enabled by the append subaddress function in the TAS5508. This function enables the
TAS5508 to append four bytes of data to a register that was opened by a previous I2C register write
operation but has not received its complete number of data bytes. Because the length of the long registers
is a multiple of four bytes, using four-byte transfers has only an integral number of append operations.
When the correct number of bytes has been received, the TAS5508 starts processing the data.
The procedure to perform an incremental multibyte-write operation is as follows:
1. Start a normal I2C write operation by sending the device address, write bit, register subaddress, and
the first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this
point, the register has been opened and accepts the remaining data that is sent by writing four-byte
blocks of data to the append subaddress (0xFE).
2. At a later time, one or more append data transfers are performed to incrementally transfer the
remaining number of bytes in sequential order to complete the register write operation. Each of these
append operations is composed of the device address, write bit, append subaddress (0xFE), and four
bytes of data followed by a stop condition.
3. The operation is terminated due to an error condition, and the data is flushed:
a.
If a new subaddress is written to the TAS5508 before the correct number of bytes are written.
b.
If more or fewer than four bytes are data written at the beginning or during any of the append
operations.
c.
If a read bit is sent.
As shown in Figure 5-4, a single-byte, data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
and then a read are actually performed. Initially, a write is performed to transfer the address byte or bytes
of the internal memory address to be read. As a result, the read/write bit is a 0. After receiving the
TAS5508 address and the read/write bit, the TAS5508 responds with an acknowledge bit. In addition, after
sending the internal memory address byte or bytes, the master device transmits another start condition
followed by the TAS5508 address and the read/write bit again. This time the read/write bit is a 1,
indicating a read transfer. After receiving the TAS5508 and the read/write bit the TAS5508 again responds
with an acknowledge bit. Next, the TAS5508 transmits the data byte from the memory address being read.
After receiving the data byte, the master device transmits a not acknowledge followed by a stop condition
to complete the single-byte, data-read transfer.
Figure 5-4. Single-Byte Read Transfer
67
I2C Serial-Control Interface (Slave Address 0x36)
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