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參數(shù)資料
| 型號： | TDA8046H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Multi-mode QAM demodulator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 文件頁數(shù)： | 17/48頁 |
| 文件大小： | 245K |
| 代理商： | TDA8046H |
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1996 Nov 19
17
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
7.1.6
AGC
The AGC estimates the mean power based on the digital
input signal and relates this to a peak value for a given
constellation. To avoid overloading of the ADC, this
estimation of the peak signals is used to control the AGC
loop. The implemented AGC covers a range of
±
20 dB in
gain variance. A schematic diagram of the AGC is
illustrated in Fig.13.
If the SAW filter does not have sufficient adjacent channel
attenuation, the AGC threshold can be varied to avoid
clipping of the ADC. To do this, the threshold is made
programmable via the I
2
C-bus (byte ATH). Table 2 shows
that for each mode, a new ATH value (on address 08)
must be set with the help of the I
2
C-bus.
The I
2
C-bus data on address 08 is a factor 16 smaller than
the used AGC threshold ATH.
The DAC output current range can be varied via the
I
2
C-bus interface (bits AGCA and AGCB) and the sign of
the current can be inverted (bit AGCI). The definition of the
DAC currents and the expected frequency behaviour of
the AGC is illustrated in Fig.14.
For characteristics see Chapter 14.
Table 2
AGC threshold values
MODE
ATH (AGC THRESHOLD)
I
2
C-BUS DATA FOR ADDRESS 08
256, 64, 16 and 4-QAM
32-QAM
2040
1442
7F
5A
Fig.13 AGC schematic diagram.
handbook, full pagewidth
DAC
rs
IBIAS
Iref2
Iref2
IAGC
Vref
external
AGC
DETECTOR
BIAS
GENERATOR
to AGC
amplifier
MGG173
ADC
I
2
C-BUS
I
2
C-BUS
I
2
C-BUS
DIN8
to
DIN0
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