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參數(shù)資料
| 型號： | TDA8046H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Multi-mode QAM demodulator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 245K |
| 代理商： | TDA8046H |
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1996 Nov 19
19
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
7.1.7
O
FFSET CONTROL
To compensate offsets in the I and Q branch, due to
spurious signals at the symbol frequency at the ADC input,
an offset compensation loop is included. This loop forces
the constellation to be symmetrically distributed over its
four quadrants. This function can be switched off by
I
2
C-bus bit OFFS.
7.1.8
L
OOP AMPLIFIERS
Analog switches are integrated to discharge the loop filter
capacitors or for test purposes on application boards (a
reference voltage equal to the half of the positive supply
voltage V
DDA
is available at the output of the amplifier
when the switches are closed). The I
2
C-bus bit ANAS
controls the three switches simultaneously. A schematic
diagram of the loop amplifier and analog switch is
illustrated in Fig.15.
For characteristics see Chapter 15.
Fig.15 Loop amplifier and analog switch.
handbook, halfpage
DAC
Vref
external
MGG174
I
2
C-BUS
7.1.9
O
UTPUT FORMATTER
The output formatter transforms the detected symbols into
bits in accordance with the selected mapping. The
TDA8046 has four possible mapping formats which can be
selected via the I
2
C-bus interface. The demapping
procedure and the corresponding bits are defined in
Fig.16. After demapping the bits are allocated to the
output. This output allocation corresponds to one of the
selected demapping schemes.
By using the I
2
C-bus, it is possible to obtain the following
output formats:
8 bits parallel
semi-serial
I and Q 8 bits multiplexed.
The implemented demapping formats and output bit
allocation are illustrated in Figs 17 to 30.
7.1.10
B
OUNDARY SCAN
The TDA8046H offers the possibility of boundary scan
test. The IEEE Standard Test Access Port and Boundary
Scan Architecture allows board manufacturers to test
board interconnections by using the boundary scan
functions.
Complete information on boundary scan test is available in
“Application note AN96048”
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