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參數(shù)資料
| 型號(hào)： | TDA8540T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 4 X 4 video switch matrix |
| 中文描述： | 4-CHANNEL, AUDIO/VIDEO SWITCH, PDSO20 |
| 文件頁(yè)數(shù)： | 9/20頁(yè) |
| 文件大?。?/td> | 131K |
| 代理商： | TDA8540T |
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1995 Feb 06
9
Philips Semiconductors
Product specification
4
×
4 video switch matrix
TDA8540
Notes
1.
2.
Only for pins 6 and 8 when clamp action is not selected for these pins.
On all the video input pins, when non-I
2
C-bus control mode is selected or when clamp action is selected on
pins 6 and 8 (by I
2
C-bus control).
Connected between V
CC
and pin 4 or pin 15.
Connected between AGND and pin 4 or pin 15.
3.
4.
CHARACTERISTICS
V
CC
= 8 V; T
amb
= 25
°
C; gain condition, clamp condition and OFF state are controlled by the I
2
C-bus;
unless otherwise specified.
Sub-address S0, S1 and S2 (pins 5, 7 and 11)
V
IH
V
IL
HIGH level input voltage
LOW level input voltage
4
0
V
CC
1
V
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
I
CC
supply current
without load
OFF state
20
12
30
mA
mA
Video inputs: IN0 to IN3 when the clamp is active
(see Figs 3 and 4)
I
LI
V
clamp
I
clamp
input leakage current
input clamping voltage
input clamping current
V
I
= 3 V
I
I
= 5
μ
A
V
I
= 0 V
1.2
0.4
2.2
1
μ
A
V
mA
Video inputs: IN0 and IN2 when the clamp is not active
(see Fig.3)
V
bias
R
I
DC input bias level
input resistance
I
I
= 0
2.9
10
V
k
Video outputs: OUT0 to OUT3
(see Fig.5)
Z
O
R
O
ISO
V
O
V
bias
output impedance
output resistance
isolation
output top sync level; (Y or CVBS)
output mean value for chrominance
signals
OFF state
100
60
0.4
1.5
1
1
5
60
36
5
0.7
1.9
1.3
0
6
0.5
0.6
0.5
70
55
1
2.2
1.6
+1
7
3
2
k
dB
V
V
V
dB
dB
%
deg
%
dB
dB
OFF state; f = 5 MHz
G = 2; load = 150
G = 1; without load
G = 1; f = 1 MHz
G = 2; f = 1 MHz
note 1
note 1
note 2
note 3
note 4
G
v
voltage gain
G
diff
diff
NL
α
ct
SVRR
differential gain
differential phase
non linearity
crosstalk attenuation between channels
supply voltage rejection
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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