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參數(shù)資料
| 型號： | TDA9874APS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 接收器 |
| 英文描述： | Digital TV sound demodulator/decoder |
| 中文描述： | AM/FM, AUDIO DEMODULATOR, PDIP42 |
| 封裝： | 0.600 INCH, SHRINK, PLASTIC, MS-020, SOT-270-1, DIP-42 |
| 文件頁數(shù)： | 31/68頁 |
| 文件大?。?/td> | 231K |
| 代理商： | TDA9874APS |
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1999 Dec 03
31
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
10.3.3
G
ENERAL
C
ONFIGURATION
R
EGISTER
(GCONR)
The default setting after power-on reset is ‘1100 0000’.
Table 17
General configuration register (subaddress 1)
Table 18
Description of the GCONR bits
7
6
5
4
3
2
1
0
P2OUT
P1OUT
STDBY
INIT
CLRPFR
AGCSLOW
AGCOFF
SIFSEL
BIT
SYMBOL
DESCRIPTION
7
6
P2OUT
P1OUT
General purpose I/O pins 1 and 2:
these bits control the general purpose input/output
pins. The contents of these bits is written directly to the corresponding pins. If an input is
desired, the bits must be set HIGH to allow the pins to be pulled LOW externally. Input
from the pins is reflected in the device status register (see Section 10.4.1). P1OUT is
recommended to be used for switching an SIF trap for the adjacent picture carrier in
designs that employ such a trap.
Standby mode on/off:
when STDBY = 1 the TDA9874A is set to the standby mode.
Most functions are disabled and power dissipation is somewhat reduced. When
STDBY = 0, the TDA9874A is in its normal mode of operation. On return from standby
mode, the device is in its Power-on reset mode and needs to be reinitialized with data
defined by the user.
Initialize to default settings:
when INIT = 1 it causes initialization of TDA9874A to its
default settings. This has the same effect as a Power-on reset. In the event of a conflict
between the default settings and any bit set HIGH in this register, the bits actually
written to this register will overwrite the default settings. This bit is automatically reset to
LOW after initialization has been completed. When set LOW, the TDA9874A is in its
normal mode of operation.
Clear power failure register:
when CLRPFR = 1 it resets the clear power failure
register. This bit is automatically reset to CLRPFR = 0 after bit PFR in the device status
register has been read.
AGC decay time:
when AGCSLOW = 1 a longer decay time and larger hysteresis are
selected for input signals with strong video modulation (conventional intercarrier). This
bit has only an effect, when bit AGCOFF = 0. When AGCSLOW = 0, it selects normal
attack and decay times for the AGC and a small hysteresis.
AGC on/off:
when AGCOFF = 1 it forces the AGC block to a fixed gain as defined in the
AGC gain register (see Section 10.3.2). When AGCOFF = 0, the AGC function is
enabled and the contents of the AGC gain register are ignored.
SIF input select:
when SIFSEL = 1 it selects pin SIF2 for input (recommended for
satellite tuner). When SIFSEL = 0, pin SIF1 (recommended for terrestrial TV) is
selected.
5
STDBY
4
INIT
3
CLRPFR
2
AGCSLOW
1
AGCOFF
0
SIFSEL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9874H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital TV sound demodulator/decoder |
| TDA9875 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital TV Sound Processor DTVSP |
| TDA9875A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital TV Sound Processor DTVSP |
| TDA9875AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital TV Sound Processor DTVSP |
| TDA9875AH/V2,557 | 功能描述:IC SOUND PROC DGTL TV 64QFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
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